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http://dx.doi.org/10.6117/kmeps.2020.27.3.089

Thermal Warpage Behavior of Single-Side Polished Silicon Wafers  

Kim, Junmo (Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST))
Gu, Chang-Yeon (Department of Mechanical Engineering, Pohang University of Science and Technology (POSTECH))
Kim, Taek-Soo (Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST))
Publication Information
Journal of the Microelectronics and Packaging Society / v.27, no.3, 2020 , pp. 89-93 More about this Journal
Abstract
Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.
Keywords
silicon wafer; warpage; digital image correlation; coefficient of thermal expansion; polishing;
Citations & Related Records
Times Cited By KSCI : 4  (Citation Analysis)
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