• Journal of the Korean institute of surface engineering
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• v.47 no.2
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• pp.68-74
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• 2014

The seed step-coverage enhancement process (SSEP) using Pd/Cu/PVP colloids was investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd/Cu nano-particles were well dispersed in aqueous solution with the average diameter of 6.18 nm. This Pd/Cu nano-particles were uniformly deposited on the substrate of Si/$SiO_2$/Ti wafer using electrophoresis with the high frequency Alternating Current (AC). After electroless Cu deposition on the substrate treated with Pd/Cu/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. The Cu deposit obtained by SSEP with Pd/Cu/PVP colloids showed superior adhesion property to that on Pd ion catalyst-treated substrate. Finally, by implementing the SSEP using Pd/Cu/PVP colloids, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free filling in high aspect ratio TSV.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.103-110
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• 2014

Recent TSV based 3D Integrated Circuit (IC) technology needs more powerful thermal management techniques. However, because cooling cost and form factor are restricted, thermal management are emphasis on software based techniques. But in case of throttling thermal management which one of the most candidate technique, increasing bus occupation induce total performance decrease. To solve communication bottleneck issue in TSV based 3D SoC, we proposed adaptive throttling technique Experimental results show that the proposed method can improve throughput by about 72% compare with minimal path routing.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.55-59
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• 2012

Defects such as voids or seams are frequently found in TSV via filling process. To achieve defect-free copper via filling, organic additives such as suppressor, accelerator and leveler were necessary in a copper plating bath. However, by-products stemming from the breakdown of these organic additives reduce the lifetime of the devices and plating solutions. In this research, the effects of levelers on copper electrodeposition were investigated without suppressor and accelerator to lower the concentration of additives. Threelevelers(janus green B, methylene violet, diazine black) were investigated to study the effects of levelers on copper deposition. Electrochemical behaviors of these levelers were different in terms of deposition rate. Filling performances were analyzed by cross sectional images and its characteristics were different with variations of levelers.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2008.11a
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• pp.18-18
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• 2008

3차원 패키징 System In Package (SIP)구조에서 Chip to Chip 단위 Interconnection 역할을 하는 Through Silicon Via(TSV)를 형성하기 위하여 Pulsating RF bias가 장착된 Inductively Coupled Plasma Etcher 장비를 이용하였다. 이 Pulsating 플라즈마 공정 방법은 주기적인 펄스($50{\sim}500Hz$)와 듀티($20{\sim}99%$) cycle 조절이 가능하며, 플라즈마 에칭특성에 영향을 주는 플라즈마즈마 발생 On/Off타임을 조절할 수 있다. 예를 들면, 플라즈마 발생 Off일 경우에는 이온(SFx+, O+)과 래디컬(SF*, F*, O*)의 농도 및 활성도를 급격하게 줄이는 효과를 얻을 수가 있는데, 이러한 효과는 식각 에칭시, 이온폭격의 손상을 급격하게 줄일 수 있으며, 실리콘 표면과 래디컬의 화학적 반응을 조절하여 에칭 측벽 식각 보호막 (SiOxFy : Silicon- Oxy- Fluoride)을 형성하는데 영향을 미친다. 그리고, TSV 형성에 있어서 큰 문제점으로 지적되고 있는 언더컷과 수평에칭 (Horizontal etching)을 개선하기 위한 방법으로, Black-Siphenomenon을 이번 실험에 적용하였다. 이 Black-Si phenomenon은 Bare Si샘플을 이용하여, 언더컷(Undercut) 및 수평 에칭 (Horizontal etching)이 최소화 되는 공정 조건을 간편하게 평가 할 수 있는 방법으로써, 에칭 조건 및 비율을 최적화하는 데 효율적이었다. 결과적으로, Pulsating RF bias가 장착된 Inductively Coupled Plasma Etcher 장비를 이용한 에칭실험은 펄스 주파수($50{\sim}500Hz$)와 듀티($20{\sim}99%$) cycle 조절이 가능하여, 이온(SFx+, O+)과 래디컬(SF*, F*, O*)의 농도와 활성화를 조절 하는데 효과적이었으며, Through Silicon Via (TSV)를 형성 하는데 있어서 Black-Si phenomenon 적용은 기존의 Continuous 플라즈마 식각 결과보다 향상된 에칭 조건 및 에칭 프로파일 결과를 얻는데 효과적이었다.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Journal of Korean Society for Atmospheric Environment
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• v.32 no.6
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• pp.624-632
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• 2016

Attention plays vital role either students academic performance in classroom or work performance of workers. This study was accomplished among elementary school students of elementary school classroom for two years. Three experiment cases were designed based on the Predicted Mean Vote (PMV) indexes. Thermal environment and PMV were directly monitored; Thermal Sensation Vote (TSV) and Comfort Sensation Vote (CSV) were analyzed based on survey data; and attention was analyzed for different comfort level using FAIR program. PMV, TSV and CSV were varied with the change in thermal environment and there was not noticeable gender influence on impact. The good correlation between thermal environment, PMV, TSV and CSV confirmed the impact of thermal environment on indoor comfort. There were different impacts on attention with comfort conditions. Academic attention of low attention group i.e. weak students, can be improved by providing the comfort environment. Thermal environment influences the comfort and the comfort influences the attention, it is possible to assess the impact of thermal environment on attention in further.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.857-863
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• 2014

In this work, we introduce various bonding technologies for 3D package and suggest Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. Microstructure of Insert-Bump bonding (ISB) specimens is investigated with respect to bonding parameters. Through experiments, we study on find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluate in the case of fluxing and no-fluxing condition. Although no-fluxing bonding process is applied to ISB bonding process, good bonding interface at $270^{\circ}C$ is formed due to the effect of oxide layer breakage.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.5-9
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• 2015

Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.10
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• pp.40-44
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• 2010

Laser drilling is an enabling technology for Through Silicon Via (TSV) interconnect applications. Recent advances in picoseconds laser drilling of blind, micron sized vias in silicon is presented here highlighting some of the attractive features of this approach such as excellent sidewall quality. In this study, we dealt with comparison of heat affection around drilled hole between a picosecond laser and a nanosecond laser process under the UV wavelength. Points which special attention should be paid are that picosecond laser process lowered experimentally recast layer, surface debris and micro-crack around hole in comparison with nanosecond laser process. These finding suggests that laser TSV process has possibility to drill under $10{\mu}m$ via. Finally, the laser drilling platform was constructed successfully.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.46-46
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• 2018

메모리 소자의 수요가 데스크톱 컴퓨터의 정체와 모바일 기기의 폭발적인 증가로 NAND flash 메모리의 고집적화로 이어져서 3차원 집적 기술의 고도화가 중요한 요소가 되고 있다. 1 mm 정도의 얇은 웨이퍼 상에 만들어지는 메모리 소자는 실제 두께는 몇 마이크로미터 되지 않는다. 수직방향으로 여러 장의 웨이퍼를 연결하면 폭 방향으로 이미 거의 한계에 도달해있는 크기 축소(shrinking) 기술에 의지 하지 않고서도 메모리 소자의 용량을 증대 시킬 수 있다. CPU, AP등의 논리 연산 소자의 경우에는 발열 문제로 3D stacking 기술의 구현이 쉽지 않지만 메모리 소자의 경우에는 저 전력화를 통해서 실용화가 시작되었다. 스마트폰, 휴대용 보조 저장 매체(USB memory, SSD)등에 수 십 GB의 용량이 보편적인 현재, FEOL, BEOL 기술을 모두 가지고 있는 국내의 반도체 소자 업체들은 자연스럽게 TSV 기술과 이에 필요한 장비의 개발에 관심을 가지게 되었다. 특히 이 중 TSV용 스퍼터링 장치는 transistor의 main contact 공정에 전 세계 시장의 90% 이상을 점유하고 있는 글로벌 업체의 경우에도 완전히 만족스러운 장비를 공급하지는 못하고 있는 상태여서 연구 개발의 적절한 시기이다. 기본 개념은 일반적인 마그네트론 스퍼터링이 중성 입자를 타겟 표면에서 발생시키는데 이를 다시 추가적인 전력 공급으로 전자 - 중성 충돌로 인한 이온화 과정을 추가하고 여기서 발생된 타겟 이온들을 웨이퍼의 표면에 최대한 수직 방향으로 입사시키려는 노력이 핵심이다. 본 발표에서는 고전력 이온화 스퍼터링 시스템의 자기장 해석, 냉각 효율 해석, 멀티 모듈 회전 자석 음극에 대한 동역학적 분석 결과를 발표한다. 그림1에는 이중 회전 모듈에 대한 다물체 동역학 해석을 Adams s/w package로 해석하기 위하여 작성한 모델이고 그림2는 180도 회전한 서브 모듈의 위상이 음극 냉각에 미치는 효과를 CFD-ACE+로 유동 해석한 결과를 나타내고 있다.