References
- J. Sun, K. Kondo, T. Okamura, S. J. Oh, M. Tomisaka, H. Yonemura and M, Hoshino, "High-Aspect-Ratio Copper Via- Filling Used for Three-Dimensional Chip Stacking", J. Electrochem. Soc., 150(6), G355 (2003). https://doi.org/10.1149/1.1572154
- M. Uemoto, K. Tanida, Y. Nemoto, M. Hoshino, K. Kojima, Y. Shirai and K. Takahashi, "High-Performance Vertical Interconnection for High-Density 3D Chip Stacking Package", Proc. 54th Electronic Components and Technology Conference (ECTC),Las Vegas, 616, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2004).
- M. Hirano, K. Nishikawa, I. Toyoda, S. Aoyama, S. Sugitani and K.Yamasaki, "Three-Dimensional Interconnect Technology for Ultra-Compact MMICs", Solid-State Electron., 41(10), 1451 (1997). https://doi.org/10.1016/S0038-1101(97)00088-9
- H. Honma, "Plating Technology for Electronics Packaging", Electrochim. Acta, 47(1-2), 75 (2001). https://doi.org/10.1016/S0013-4686(01)00591-6
- S. Balakumar, R. Kumar, Y. Shimura, K. Namiki, M. Fujimoto, H. Toida, M. Uchida and T. Hara, "Effect of Stress on the Properties of Copper Lines in Cu Interconnects", Electrochem. SolidSt., 7(4), G68 (2004). https://doi.org/10.1149/1.1647994
- S. E. Lee and J. H. Lee, "Copper Via Filling Using Organic Additives and Wave Current Electroplating", J. Microelectron. Packag. Soc., 14(3), 37 (2007).
- J. S. Bae, G. H. Chang and J. H. Lee, "Electroplating of Copper Using Pulse-Reverse Electroplating Method for SiP Via Filling", J. Microelectron. Packag. Soc., 12(2), 129 (2005).
- B. H. Choi, W. J. Lee and J. H. Lee, "Effects of Electroplating Parameters on the Defects of Copper Via for 3D SiP", Sol. St. Phenon., 124-126, 49 (2007). https://doi.org/10.4028/www.scientific.net/SSP.124-126.49
- W. P. Dow, C. C. Li, M. W. Lin, G. W. Su and C. C. Huang, "Copper Fill of Microvia Using a Thiol-Modified Cu Seed Layer and Various Levelers", J. Electrochem. Soc., 156(8), D314 (2009). https://doi.org/10.1149/1.3147273
- K. I. Popov. M. D. Maksimovic, M. G. Pavlovic and G. R. Ostojic, "Formation of Powdered Copper Deposits by Square- Wave Pulsating Overpotential", J. Appl. Electrochem., 7(4), 331 (1977). https://doi.org/10.1007/BF01059174
- T. P. Moffat, D. Wheeler, S. K. Kim and D. Josell, "Curvature Enhanced Adsorbate Coverage Mechanism for Bottom-Up-Superfilling and Bump Control in Damascene Processing", Electrochim. Acta, 53(1), 145 (2007). https://doi.org/10.1016/j.electacta.2007.03.025
- L. Hofmann, R. Ecke, S. E. Schulz and T. Gessner, "Investigations Regarding Through Silicon Via Filling for 3D Integration by Periodic Pulse Reverse Plating with and without Additives", Microelectron. Eng., 88(5), 705 (2011). https://doi.org/10.1016/j.mee.2010.06.040
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