• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.61-68
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• 2004

Today almost all chips have IEEE 1149.1 tap controller inside. Recently the circuit is embedded in the chips for other functional objectives. Hence a CED technique for testing and monitoring the IEEE 1149.1 tap controller had been proposed. This paper studies the optimal CED test technique on the IEEE 1149.1 tap controller. There are duplication, parity prediction, and hybrid techniques. The hybrid technique shows the best result on the area overhead. This means that the hybrid technique is perfectly adequate for the IEEE 1149.1 tap controller to be applied to test with the optimal area overhead and can be used widely in the field. Furthermore, we made more reduction from the previous method resulting in less area overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.85-92
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• 2004

A design of a preceding instruction decoding module(PIDM) is proposed aiming at performance enhancement of JTAG-based test complying to the IEEE 1149.1 standard. The PIDM minimizes the number of clocks by performing test access port(TAP) instruction decoding process prior to the execution of TAP-controlled test activities. The scheme allows the generation of signals such as test mode select(TMS) inside of a target system. The design employing PIDM demonstrates 15% performance enhancement with simulation of a CORDIC processor and 48% reduction of the TAP-controller's circuit size with respect to the conventional design of a non-PIDM version.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.226-232
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• 2005

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some 14% performance enhancement and 50% gate count reduction compared to the conventional ones.

• Journal of Electrical Engineering and Technology
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• v.4 no.3
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• pp.330-336
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• 2009

This paper proposes an on-line voltage management and control solution for a distribution system which can improve the efficiency and accuracy of existing off-line work by collecting customer voltage on-line as well as the voltage compensation capability of the existing ULTC (Under Load Tap Changer) operation and control strategy by controlling the ULTC tap based on pattern clustering and recognition. The proposed solution consists of an ADVMD (Advanced Digital Voltage Management Device), a VMS (Voltage Management Solution) and an OLDUC (On-Line Digital ULTC Controller). An on-line voltage management emulator based on multi-thread programming and the shared memory method is developed to emulate on-line voltage management and digital ULTC control methodology based on the on-line collection of the customer's voltage. In addition, using this emulator, the effectiveness of the proposed pattern clustering and recognition based ULTC control strategy is proven for the worst voltage environments for three days.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.113-114
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• 2018

ITER TF AC/DC Converter는 2Quadrant 동작하며 컨버터 변압기의 무부하 Tap chage position에 따라 출력 전압은 ${\pm}160V/68000A$, ${\pm}650V/68000A$ 2가지 출력 사양으로 동작한다. TF Local Controller는 2상한 동작과 변압기 Tap change 제어에서 높은 신뢰도를 요구 한다. 본 논문은 RTDS를 이용하여 TF 컨버터 제어기의 성능을 검증한 내용을 논의하고자 한다.

• Proceedings of the IEEK Conference
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• summer
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• pp.61-65
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• 2004

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage reducing overall debugging time. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some $14\%$ performance enhancement and $50\%$ gate count reduction compared to the conventional ones.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.1
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• pp.36-43
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• 2003

This paper presents an optimal tuning method for Fuzzy Logic Controller (FLC) of current controller for HVDC using Genetic Algorithm(GA). GA is probabilistic search method based on genetics and evolution theory. The scaling factors of FLC are tuned by using real-time GA. The proposed tuning method is applied to the scaled-down HVDC simulator at Korea Electrotechnology Research Institute(KERI). Experimental result shows that disturbances are well-damped and the dynamic performances of FLC have the better responses than those of PI controller for small and large disturbances such as ULTC tap change, reference DC current change and DC ground fault.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.12
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• pp.2206-2214
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• 2011

LDC(Line Drop Compensation) is widely used in controlling ULTC(Under Load Tap Changer) output voltage at distribution substation. However, LDC may experience some difficulties in voltage control due to renewable energy resources and distributed generations. Therefore, more advanced voltage control algorithm is necessary to deal with these problems. In this paper, a modified voltage control algorithm for ULTC and DG is suggested. ULTC is operated with the voltages measured at various points in distribution system and prevents overvoltage and undervoltage in the distribution feeders. Reactive power controller in DG compensates the voltage drop in each distribution feeders. By these algorithms, the voltage unbalance between feeders and voltage limit violation will be reduced and the voltage profile in each feeder will become more flat.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.293-296
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• 2012

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a system-on- a-chip (SOC) is controlled by test access ports (TAP) and TAP controller of IEEE standard 1149.1 as well as tested using IEEE standard 1500. An SOC device including TAPed cores is hierarchically organized by IEEE standard 1149.7 in wafer and chip level. As a result, it is possible to select/deselect all cores embedded in an SOC flexibly and reduce test cost dramatically using star scan topology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.728-734
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• 2001

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects at system speed. Experimental design shows that the technique proposed requires much less area than a commercial approach.