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Preceding Instruction Decoding Module(PIDM) for Test Performance Enhancement of JTAG based Systems  

윤연상 (충북대학교 정보통신공학과)
김승열 (충북대학교 정보통신공학)
권순열 (충북대학교 정보통신공학)
박진섭 (충북대학교 정보통신공학)
김용대 (충북대학교 정보통신공학)
유영갑 (충북대학교 정보통신공학과)
Publication Information
Abstract
A design of a preceding instruction decoding module(PIDM) is proposed aiming at performance enhancement of JTAG-based test complying to the IEEE 1149.1 standard. The PIDM minimizes the number of clocks by performing test access port(TAP) instruction decoding process prior to the execution of TAP-controlled test activities. The scheme allows the generation of signals such as test mode select(TMS) inside of a target system. The design employing PIDM demonstrates 15% performance enhancement with simulation of a CORDIC processor and 48% reduction of the TAP-controller's circuit size with respect to the conventional design of a non-PIDM version.
Keywords
TMS signal generator; JTAG boundary scan test; CORDIC;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 K. P. Parker, The Boundary Scam Handbook, Kluwer2003 Academic Publishers,
2 S. Furber, ARM System-on-Chip Architecture, 2nd Ed., Addison Wesley, 2000
3 Advanced RISC Machines, ARM7TDMI Data Sheet, Document Number: ARMDDI0029E, http://www.arm.com
4 김승열, 김용대, 한선경, 유영갑, 'Redundant Signed Binary Number에 의한 CORDIC 회로,' 대한전자공학회논문지, 40권, CI편, 6호, 317-324쪽, 2003년 11월   과학기술학회마을
5 IEEE Std 1149.1-2001,Test Port and Boundary-Scan Architecture, IEEE, 2001
6 I. Huang, C. Kao and H. Chen, 'A Retargetable Embedded In Circuit Emulation Module for Microprocessors,' IEEE Design & Test of Computers, vol. 19, pp. 28-38, Aug. 2002   DOI   ScienceOn
7 C. MacNamee, D. Heffernan, 'Emerging On-Chip Debugging Techniques for Real-Time Embedded Systems,' IEE Computing & Control Eng., vol. 11, no. 6, pp. 295-303, Dec. 2000   DOI   ScienceOn