• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.10 s.241
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• pp.1298-1306
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• 2005

In this paper, Part II, we realized the Serpentine Laminating Micromirer (SLM) which was proposed in the accompanying paper, Part I, by means of the injection molding process in mass production. In the SLM, the higher level of chaotic mixing can be achieved by combining two general chaotic mixing mechanisms of splitting/recombination and chaotic advection by the successive arrangement of 'F'-shape mixing units in two layers. Mold inserts for the injection molding process of the SLM were fabricated by SU-8 photolithography and nickel electroplating. The SLM was realized by injection molding of COC (cyclic olefin copolymer) with the fabricated mold inserts and thermal bonding of two injection molded COC substrates. To compare the mixing performance, a T-type micromixer was also fabricated. Mixing performances of micromixers were experimentally characterized in terms of an average mixing color intensity of a pH indicator, phenolphthalein. Experimental results show that the SLM has much better mixing performance than the I-type micromixer and chaotic mixing was successfully achieved from the SLM over the wide range of Reynolds number (Re). The chaotic micromixer, SLM proposed in this study, could be easily integrated in Micro-Total-Analysis- System , Lab-on-a-Chip and so on.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.826-832
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• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.509-517
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• 2001

Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.747-749
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• 2012

This paper is analyzing the SoC policy of major nations as the U.S, Japan, Europe, Taiwan, China and draw the suggestions for the development of semiconductor industry in Korea. SoC is the non-memory semiconductor to support and put into action the function of system. SoC is big market over the 200billion dollars and have a huge potential for new IT convergence market. Developed countries as the US, Japan, and Europe have enforced the industrial competitiveness by company investment and Taiwan supported the SoC Industry by government fund. Korea is No.1 superpower in DRAM semiconductor, but very weak in SoC Industry. We should secure the competitiveness of SoC Industry by the development of core technology, planning the growth policy, and building the cooperative model to leap the SoC power nation.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.23-30
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• 2007

RFID it reads information which is it writes, the semiconductor chip for and the radio frequency system which uses the hazard antenna it has built-in transmission of information it talks. Formation which is transmitted like this collection and America which it filtrates wey the RFID search service back to inform the location of the server which has commodity information which relates with an object past record server. The hazard where measurement analysis result the leader for electronic interference does not occur consequently together from with verification test the power level which is received from the antenna grade where it stands must maintain minimum -55dBm and the electronic interference will not occur with the fact that, antenna and reel his recognition distance the maximum 7m until the recognition which is possible but smooth hazard it must stand and and with the fact that it will do from within and and and 3-4m it must be used Jig it is thought.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.213-218
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• 2008

This paper describes hardware-based high speed multimedia data reassembly processor for remote multimedia Set-Top-Box(MSTB) of interactive satellite multimedia communication system. The conventional multimedia data reassembly scheme is based on software processing of MSTB. As increasing of transmission rate for multimedia data services, the CPU load of remote MSTB is increased and reassembly performance of MSTB is limited. To provide high speed multimedia data service to end user, we proposed hardware based high speed multimedia data reassembly processor. It is implemented by using an FPGA, a PCI interface chip, and RAMs. And it is integrated in MSTB and tested. It has been confirmed to meet required all functions and processing rate up to 116Mbps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.3
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• pp.453-460
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• 2014

Fault injection attack is the process of attempting to acquire the information on-chip through inject artificially generated error code into the cryptographic algorithms operation (or perform) which is implemented in hardware or software. From the details above, the laser-assisted failure injection attacks have been proven particularly successful. In this paper, we propose an improved laser probing system for fault injection attack which is called the Dual-Laser FA tool set, a hybrid approach of the Flash-pumping laser and fiber laser. The main concept of the idea is to improve the laser probe through utilizing existing equipment. The proposed laser probe can be divided into two parts, which are Laser-I for laser cutting, and Laser-II for fault injection. We study the advantages of existing equipment, and consider the significant parameters such as energy, repetition rate, wavelength, etc. In this approach, it solves the high energy problem caused by flash-pumping laser in higher repetition frequency from the fiber laser.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2337-2342
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• 2010

There is a vast field of application for RFID(Radio Frequency IDentification) technology. In the case of hospitals, RFID can be used for organizing patient data. Generally, patient data has been handled with medical cards. In order to look up data about a patient, the medical card would have to be found first, within a lot of other medical cards, by hand or with a computer. This is a very inconvenient system. Also, if the card is searched by the name of the patient, fatal medical accidents may occur in cases of mix-ups. If remote RFID Tag monitoring systems are applied in this case, the patient data would be accessible in the hospital. This article will discuss the grafting of RFID systems and wireless data communicating technology. The EM4095 chip, which uses 125KHz carrier waves was used in this study. And a Bluetooth module was added for wireless data communication. The ATMEGA128 microcomputer was used to control the RFID system and wireless module. A LCD monitor was connected to the extension port for nurses to view patient data, and also, the same information was displayed on PC monitors for doctors to see. The circuit was designed to consume minimal amounts of electricity for portability, and to transmit Tag ID's in environments with a lot of noise. The article is concluded with a diagram of the whole system, and performance of each data transmitting section has been analyzed.