• Journal of Semiconductor Engineering
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• v.1 no.3
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• pp.81-87
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• 2020

An instrumentation amplifier (IA) and an analog-to-digital converter (ADC) are essential circuit blocks for accurate and robust sensor readout systems. This paper introduces recent advances in radiation-hardening by design (RHBD) techniques applied for the sensor readout integrated circuits (IC), e.g., the three-op-amp IA and the successive-approximation register (SAR) ADC, operating against total ionizing dose (TID) and singe event effect (SEE) in harsh radiation environments. The radiation-hardened IA utilized TID monitoring and adaptive reference control to compensate for transistor parameter variations due to radiation effects. The radiation-hardened SAR ADC adopts delay-based double-feedback flip-flops to prevent soft errors which flips the data bits. Radiation-hardened IA and ADC were verified through compact model simulation, and fabricated CMOS chips were measured in radiation facilities to confirm their radiation tolerance.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.99-108
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• 2021

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.1
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• pp.202-215
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• 2023

This paper proposes a non-orthogonal multiple access (NOMA) based low-complexity relaying approach for multiuser cellular two-way relay channels (CTWRCs). In the proposed scheme, the relay detects the signal using successive interference cancellation (SIC) and re-generates the transmit signal with zero-forcing (ZF) transmit precoding. The achievable data rates of the NOMA-based multiuser two-way relaying (TWR) approach is analyzed. We further study the power allocation among different data streams to maximize the weighted sum-rate (WSR). We re-form the resultant non-convex problem into a standard monotonic program. Then, we design a polyblock outer approximation algorithm to sovle the WSR problem.The proposed optimal power allocation algorithm converges fast and it is shown that the NOMA-TWR-OPA scheme outperforms a NOMA benchmark scheme and conventional TWR schemes.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.134-138
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• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.6
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• pp.3813-3820
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• 2014

Recently, with the increase in electrical consumption and the unbalanced power demand and supply, the power reserve rate is becoming smaller and the reliability of the power supply is deteriorating. Under this circumstance, a Battery Energy Storage System (BESS) is considered to be an essential countermeasure for demand side management. On the other hand, an economic evaluation is a critical issue for the introduction of a power system because the cost of BESS is quite high. Therefore, this paper presents economic evaluation method for utility use by considering the best mix method and successive approximation method, and an economic evaluation method for customer use by considering the peak shaving function based on the real time price. From a case study on a model power system and educational customer, it was confirmed that the proposed method is a practical tool for the economic analysis of BESS.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• The Journal of the Acoustical Society of Korea
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• v.25 no.7
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• pp.339-345
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• 2006

We suggest new 2D two-way Parabolic equation algorithm for multiple scattering. Our method is based on the successive performance of the single scattering approach. First. as the single scattering algorithm, the reflected and transmitted fields are calculated at the vertical interface of a range independent sector. Then. the reflected field is saved and the transmitted field Propagated to the next vertical interface with the split-step Pade method. After one step ends, the same Process is repeatedly performed with the change of the Propagation direction until the reflected field at the vertical interface is close to zero. Final incoming and outgoing fields are obtained as the sum of the wave fields obtained for each step. Our algorithm is relatively simple for the numerical implementation and requires less computational resources than the existing algorithm for multiple scattering

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.2
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• pp.1-10
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• 2016

In this paper, we present a new way to derive the mean cycle time of the G/G/m failure prone queue when the loading of the system approaches to zero. The loading is the relative ratio of the arrival rate to the service rate multiplied by the number of servers. The system with low loading means the busy fraction of the system is low. The queueing system with low loading can be found in the semiconductor manufacturing process. Cluster tools in semiconductor manufacturing need a setup whenever the types of two successive lots are different. To setup a cluster tool, all wafers of preceding lot should be removed. Then, the waiting time of the next lot is zero excluding the setup time. This kind of situation can be regarded as the system with low loading. By employing absorbing Markov chain model and renewal theory, we propose a new way to derive the exact mean cycle time. In addition, using the proposed method, we present the cycle times of other types of queueing systems. For a queueing model with phase type service time distribution, we can obtain a two dimensional Markov chain model, which leads us to calculate the exact cycle time. The results also can be applied to a queueing model with batch arrivals. Our results can be employed to test the accuracy of existing or newly developed approximation methods. Furthermore, we provide intuitive interpretations to the results regarding the expected waiting time. The intuitive interpretations can be used to understand logically the characteristics of systems with low loading.

• International Journal of CAD/CAM
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• v.4 no.1
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• pp.33-45
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• 2004

In this work, a rational procedure has been formulated for the selection of points approximating slice contours cut in LOM (Laminated Object manufacturing) with first order approximation. It is suggested that the number of points representing a slice contour can be 'minimised' or 'optmised' by equating the horizontal chordal deviation (HCD) to the user-defined surface form tolerance. It has been shown that such optimization leads to substantial reduction in slice height calculations and NC codes file size for cutting out the slices. Due to optimization, the number of contour points varies from layer to layer, so that points on successive layer contours have to be matched by four sided ruled surface patches and triangular patches. The technological problems associated with the cutting out of triangular patches have been addressed. A robust algorithm has been developed for the determination of slice height for optimum and arbitrary numbers of contour points with different strategies for error calculations. It has been shown that optimisation may even lead to detection and appropriate representation of elusive surface features. An index of optimisation has been defined and calculations of the same have been tabulated.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.