• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.407-410
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• 1987

A layout design concept which suppress the substrate current generated during the switching transients of an CMOS inverter is presented. The amount of hot carriers and the peak value of substrate current can be reduced by changing the device geometry ratio of driver and load device of an CMOS inverter.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1101-1104
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• 2003

In this paper, we analyzed the gate current and substrate current by the hot carrier effects and restoration phenomenon of characteristics by time in the p-channel MOSFETs. The Stress voltage condition is a voltage in maximum gate current and time is 3s, 10s, 30s, l00s, 1000s, 2000s and 3000s. As results of analysis, the gate current and substrate current were decreased by stress time, and the restoration time of characteristics were shown the results that were decreased by the exponential times.

• 대한전자공학회논문지
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• 제27권6호
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• pp.895-900
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• 1990

With the MOS device scailing down, the substrate concentration must increase in order to avoid punchthrough leakage current due to the DIBL(Drain Induced Barrier Lowering) effect. However the enhancement of the substrate concentration increases source, drain juntion capacitances and substrate current due to hot elelctron, degrading the speed characteristics and reliability of the MOS devices. In this paper, a new device, called CODE(Channel Only Dopant Enhancement) MOS, an its fabrication are proposed. By comparing the fabricated CODE MOSFET with the conventional device, the improvements on DIBL, substrate current and source, drain juntion capacitances are realized.

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.706-710
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• 2008

The substrate bias effect on the current level of SOI-MOSFETs for high temperature operation has been investigated. In this work, we demonstrate the current level of SOI-MOSFETs can be controlled at different temperatures by applying a control bias to the substrate, showing that all current levels below T=150$^{\circ}C$ can be adjusted to a constant current level. 2D numerical simulation results show that substrate bias effectively controls the current conduction; as the substrate bias effectively lower the potential of the channel, inversion carrier generation is effectively controlled and consequently a constant current conduction level is achieved up to T=150$^{\circ}C$. We also demonstrate that the device simulated in this work has same operation at any temperature below T=150$^{\circ}C$ through mixed mode simulation.

• Corrosion Science and Technology
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• 제8권3호
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• pp.93-102
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• 2009

The direct-current electroetching of high purity aluminum in hot aqueous-chloride solution produces a high density of micrometer-wide tunnels whose walls are made up of the {100} planes and penetrate aluminum in the <100> directions at rates of micrometer per second. In the process of the alternating-current pitting of aluminum, cathodic polarization plays an important role in the nucleation and growth of the pits during the subsequent polarization. The direct-current tunnel etching and alternating-current etching of aluminum are basically related to the formation of poorly crystallized or amorphous passive films. If the passive film forms on the wall, a natural misfit exists between the film and the aluminum substrate, which in turn gives rise to stress in both the film and the substrate. Even though the amorphous films do not have directed properties, their stresses are influenced by the substrate orientation. The films on elastically soft substrate are likely to be less stressed and more stable than those on elastically hard substrate. The hardest and softest planes of aluminum are the {111} and {100} planes, respectively. Therefore, the films on the {111} substrates are most likely to be attacked, and those on the {100} substrates are least likely to be attacked. For the tunnel etching, it follows that the tunnel walls tend to consist of the {100} planes. Meanwhile, the tunnel tip, where active corrosion takes place, tend to be made of four closely packed {111} planes in order to minimize the surface energy, which gives rise to the <100> tunnel etching.

• EDISON SW 활용 경진대회 논문집
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• 제3회(2014년)
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• pp.415-419
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• 2014

나노스케일 MOSFET에서 leakage current는 중요한 이슈로서 $Si_{1-x}Ge_x$ alloy를 substrate로 사용할 경우 leakage current에 어떤 영향을 미칠 것인지 시뮬레이션을 통하여 알아보았다. $Si_{1-x}Ge_x$ alloy에서 Ge의 비율이 증가할수록 유효질량이 작아졌으나 conduction band minimum의 위치는 Si에 비해 상승하였다. 이로 인해 tunneling 확률이 증가하여 $Si_{1-x}Ge_x$ alloy를 substrate로 사용할 경우 leakage current를 더욱 증가시키게 되었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권10호
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• pp.505-509
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• 2004

The (Sr/sub 0.9/Ca/sub 0.1/)TiO₃(SCT) thin films are deposited on Pt-coated electrode(Pt/TiN/SiO₂/Si) using RF sputtering method at various substrate temperature. The optimum conditions of RF power and Ar/O₂ ratio were 140[W] and 80/20, respectively. Deposition rate of SCT thin film was about 18.75[Å/min]. The crystallinity of SCT thin films were increased with increase of substrate temperature in the temperature range of 100～500[℃]. The dielectric constant of SCT thin films were increased with the increase of substrate temperature, and changed almost linearly in temperature ranges of -80～+90[℃]. The current-voltage characteristics of SCT thin films showed the increasing leakage current as the substrate temperature increases.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.191-193
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• 2006

YBCO wire has a metal substrate to improve the texture structure and highly conductive layers to increase the cryogenic stability. When AC current flows in the YBCO wire, magnetic field which is generated by the AC current magnetizes the metal substrate and induces the eddy current in the stabilizing layer. To examine the effect of the metal substrate and the conducting layer on the transport current loss of YBCO wire, this paper presents the transport current loss of YBCO wire which has metal substrate and conductive layer. YBCO wire with Ni-W substrate and copper layer were chosen as the model HTS wire for numerical calculation. Finite element method has been used to calculate the transport loss and the results of numerical calculation was compared with analytic calculation suggested by Norris.

• 한국재료학회지
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• 제24권7호
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• pp.344-350
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• 2014

Metal films (i.e., Ti, Al and SUH310S) were prepared in a magnetron sputtering apparatus, and their cross-sectional structures were investigated using scanning electron microscopy. The apparatus used consisted of a cylindrical metal target which was electrically grounded, and two anode rings attached to the top and to the bottom of the target. A wire was placed along the center-line of the cylindrical target to provide a substrate. When the electrical potential of the substrate was varied, the metal-film formation rate depended on both the discharge voltage and the electrical potential of the substrate. As we made the magnetic field stronger, the plasma which appeared near the target collected on the plasma wall surface and thereby decreased the bias current. The bias current on the conducting wire was different from that for cation collection. The bias current decreased because the collection of cations decreased when we increased the magnetic-coil current. When the substrate was electrically isolated, the films deposited showed a slightly coarse columnar structure with thin voids between adjacent columns. In contrast, in the case of the grounded substrate, the deposited film did not show any clear columns but instead, showed a densely-packed granular structure. No peeling region was observed between the film and substrate, indicating good adhesion.

• ETRI Journal
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• 제31권6호
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• pp.725-731
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• 2009

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate-triggered NMOS and a gate-substrate-triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn-on speed. The proposed ESD protection devices are designed using 0.13 ${\mu}m$ CMOS technology. The experimental results show that the proposed substrate-triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn-on time of 37 ns. The proposed gate-substrate-triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.