• Journal of the Korean Society of Marine Environment & Safety
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• v.2 no.1
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• pp.35-45
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• 1996

The assesment of the safety of ship's transit in a curved narrow channel consists of the maneuvering safety determined by the chance of running aground, the maneuvering difficulty determined by ship's workload, and shiphandler's subjective evaluation. In this study to examine the correlation between shiphandler's subjective evaluation and the maneuvering risk, the real-time and full-mission shiphandling simulator in the Korea Marine Training & Research Institutes(KMTRI) was utilized. On the conning bridge of the shiphandling simulator, 50 experienced masters conducted the modeled vessel of 60,000 deadweight tonnage along the designed channel under 3 different environmental conditions. The findings were as follows : (1) The frequencies of stress levels, work difficulties, vessel controllability and overall workload of shiphandlers are similar irrespective of environmental conditions and they are able to be represented as shiphandler's subjective evaluation. (2) It s possible to assess and analyze theoretically the correlation between the shiphandler's subjective evaluation and maneuvering risk under each environmental condition by quantifying the data obtained from the test. The results are as follows : ① As the degree of maneuvering risk increases, the shiphandler's subjective evaluation increases sharply near the curvature area of the designed channel. ② In the area of the curvature of the designed channel, maneuvering risk sincreases sharply with the danger of running aground under the environmental condition of current and wind coming from the stern.

• Journal of Sensor Science and Technology
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• v.12 no.5
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• pp.218-224
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• 2003

The devices of n-channel poly silicon thin film transistors(TFTs) hydrogenated by plasma, $H_2$ and $H_2$/plasma processes are fabricated. The carriers sensitivity characteristics are analyzed with voltage bias stress at the gate oxide. The parametric sensitivity characteristics caused by electrical stress conditions in hydrogenated devices are investigated by measuring the drain current, threshold voltage($V_{th}$), subthreshold slope(S) and maximum transconductance($G_m$) values. As a analyzed results, the degradation characteristics in hydrogenated n-channel polysilicon thin film transistors are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The generation of traps in gate oxide are mainly dued to hot electrons injection into the gate oxide from the channel region.

• Journal of the Korean Society of Marine Environment & Safety
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• v.2 no.S1
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• pp.63-73
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• 1996

The assesment of the safety of ship's transit in a curved narrow channl consists of the maneuvering safety determined by the chance of running aground, the maneuvering difficulty determined by shop's workload, and shiphandler's subjective evaluation. In this study to examine the correlation between shiphandler's subjectice evaluation and the maneuvering risk, the real-time and full-mission shiphandling simulator in the Korean Marine Training & Research Institutes(KMTRI) was utilized. In the conning bridge of the shiphandling simulator, 50 experienced masters conducted masters conducted the modeled vessel of 60,000 deadweight tonnage along the designed channel under 3 different envrinmental conditions. The findings were as follows: (1) The frequencies of stress levels, work difficulties, vessel controllability and overall workload of shiphandlers are similar irrespective of environmental conditions and they are able to be represented as shiphandler's subjective evaluation. (2) It is possible to assess and analyze theoretically the correlation between the shiphandler's subjective ecaluation and maneuvering risk each environmental cindition by quantifying the data obtioned from the tests. The results are as follows: ① As the degree of maneuvering risk increases, the shiphandler's subjective evaluation increases sharply near the curvature area of the desgined channel. ② In the area of the curvature of the designed channel, maneuvering risk increases sharply with the danger of running aground under the environmental condition of current and wind comung from the stem.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.21-29
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• 2004

Hot carrier degradation characteristics of Nano-scale CMOSFETs with dual gate oxide have been analyzed in depth. It is shown that, PMOSFET lifetime dominate the device lifetime than NMOSFET In Nano-scale CMOSFETs, that is, PMOSFET lifetime under CHC (Channel Hot Carrier) stress is much lower than NMOSFET lifetime under DAHC (Dram Avalanche Hot Carrier) stress. (In case of thin MOSFET, CHC stress showed severe degradation than DAHC for PMOSFET and DAHC than CHC for NMOSFET as well known.) Therefore, the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor in upcoming Nano-scale CMOSFET technology. In case of PMOSFETs, CHC shows enhanced degradation than DAHC regardless of thin and thick PMOSFETs. However, what is important is that hot hole injection rather than hot electron injection play a important role in PMOSFET degradation i.e. threshold voltage increases and saturation drain current decreases due to the hot carrier stresses for both thin and thick PMOSFET. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method. Therefore, suppression of PMOSFET hot carrier degradation or hot hole injection is highly necessary to enhance overall device lifetime or circuit lifetime in Nano-scale CMOSFET technology

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.729-732
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• 2006

The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.

• Proceedings of the Korean Biophysical Society Conference
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• 1998.06a
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• pp.39-39
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• 1998

Stretch-activated ion channel that is open by mechanical stress applied on the cell membrane is one of the classes of ion channels. Other than stretch-activated channel itself, it has been also reported that a variety of ion channels could be modulated by a mechanical cell stretch.(omitted)

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.163-163
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• 2015

The effect of nematic liquid crystal(5CB-4-Cyano-4'-pentylbiphenyl) on the amorphous indium gallium zinc oxide thin film transistors(a-IGZO TFTs) was investigated. Through dropping the 5CB on the a-IGZO TFT's channel layer which is deposited by RF-magnetron sputtering, properties of a-IGZO TFTs was dramatically improved. When drain bias was induced, 5CB molecules were oriented by Freedericksz transition generating positive charges to one side of dipoles. From increment of the capacitance by orientation of liquid crystals, the drain current was increased, and we analyzed these phenomena mathematically by using MOSFET model. Transfer characteristic showed improvement such as decreasing of subthreshold slope(SS) value 0.4 to 0.2 and 0.45 to 0.25 at linear region and saturation region, respectively. Furthermore, in positive bias system(PBS), prevention effect for electron trapping by 5CB liquid crystal dipoles was observed, which showing decrease of threshold voltage shift [(${\delta}V$]_TH) when induced +20V for 1~1000sec at the gate electrode.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.327-330
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• 2004

It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.