• 마이크로전자및패키징학회지
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• 제17권3호
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• pp.33-41
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• 2010

Crack propagation mechanisms of Sn-3.0Ag-0.5Cu solder were studied in strain controlled push-pull creepfatigue conditions using the fast-fast (pp) and the slow-fast (cp) strain waveforms at 313 K. Transgranular cracking was found in the pp strain waveform which led to the cycle-dominant crack propagation and intergranular cracking in the cp strain waveform that led to the time-dominant crack propagation. The time-dominant crack propagation rate was faster than the cycle-dominant crack propagation rate when compared with J-integral range which resulted from the creep damage at the crack tip in the cp strain waveform. Clear recrystallization around the crack was found in the pp and the cp strain waveforms, but the recrystallized grain size in the cp strain waveform was smaller than that in the pp strain waveform. The cycle-dominant crack propagated in the normal direction to the specimen axis macroscopically, but the time-dominant crack propagated in the shear direction which was discussed in relation with shear micro cracks formed at the crack tip.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• 한국항공우주학회지
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• 제49권8호
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• pp.661-669
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• 2021

종래 우주용 전장품 개발과정에서는 발사진동환경에 대한 탑재 전자소자 솔더 접합부의 피로수명 보장을 위해 기판 상에 보강재를 적용하여 강성을 증가시킴으로써 기판의 동적거동을 최소화하였다. 그러나 종래의 설계는 전장품의 부피 및 무게의 증가를 야기하여 소형/경량화 설계에 한계를 갖는다. 선행 연구에서 제안된 점탄성 테이프 기반 고댐핑 적층형 전자기판은 굽힘변위 저감을 통한 소자의 피로수명 연장에 효과적임을 입증하였으나 고댐핑 부여를 위한 적층구조가 기판에 직접 장착되는 관계로 소자 실장 공간의 효율이 저하되는 한계를 지닌다. 본 연구에서는 전장품 소형/경량/고집적화 설계 구현을 위해 일반 금속 대비 높은 댐핑과 복원 특성을 갖는 초탄성 형상기억합금에 점탄성 테이프를 적용한 적층구조의 초탄성 형상기억합금 보강재 기반 고댐핑 전자기판을 제안하였다. 제안 기판의 기본특성 파악을 위해 정하중시험 및 자유진동시험을 수행하였으며, 랜덤진동시험을 통해 진동환경 하 고댐핑 특성 및 설계 유효성을 입증하였다.

• 한국생산제조학회지
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• 제22권3_1spc호
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• pp.504-508
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• 2013

This paper describes in detail the life prediction models and simulations of thermal fatigue under different mold compounds and chip sizes for wafer-level embedded SiP. Three-dimensional finite element models are built to simulate the viscoplastic behaviors for various mold compounds and chip sizes. In particular, the bonding parts between a mold and silicon nitride (Si3N4) are carefully modeled, and the strain distributions are studied. Three different chip sizes are used, and the effects of the mold compounds are observed. Through the numerical studies, it is found that type-C, which has a relatively lower Young's modulus and higher CTE, has a better fatigue life than the other mold compounds. In addition, the $4{\times}4$ chip has a shorter life than the $6{\times}6$ and $8{\times}8$ chips.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.147-163
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• 2003

European Union bans the usage of Pb in electronics from July 1 st, 2006. The Near-eutectic Sn-Ag-Cu alloys are the leading candidate Pb-free solders (for SMT card assembly). .The microstructure of Sn-Ag-Cu alloys is discussed in terms of solidification, composition and cooling rate. Methods of controlling Ag3Sn plates are discussed. .Thermo-mechanical fatigue behaviors of Sn-Ag-Cu solder joints are reviewed. Tin pest, whisker growth, electromigration of Pb-free solders are discussed.

• Journal of Welding and Joining
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• 제29권1호
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• pp.46-51
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• 2011

TSV technology raises several reliability concerns particularly caused by thermally induced stress. In traditional package, the thermo-mechanical failure mostly occurs as a result of the damage in the solder joint. In TSV technology, however, the driving failure may be TSV interconnects. In this study, the thermomechanical reliability of TSV technology is investigated using finite element method. Thermal stress and thermal fatigue phenomenon caused by repetitive temperature cycling are analyzed, and possible failure locations are discussed. In particular, the effects of via size, via pitch and bonding pad on thermo-mechanical reliability are investigated. The plastic strain generally increases with via size increases. Therefore, expected thermal fatigue life also increase as the via size decreases. However, the small via shows the higher von Mises stress. This means that smaller vias are not always safe despite their longer life expectancy. Therefore careful design consideration of via size and pitch is required for reliability improvement. Also the bonding pad design is important for enhancing the reliability of TSV structure.

• 마이크로전자및패키징학회지
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• 제17권1호
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• pp.9-17
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• 2010

본 논문은 $20^{\circ}$ 각도의 굽힘과 50 ${\mu}m$ 인장조건에서 PGA (Pin Grid Array) 패키지의 lead pin에 발생하는 von Mises 응력과 전 변형률 에너지 밀도를 lead pin 소재의 열처리 온도 조건에 따라 유한요소법을 이용하여 해석하였다. 해석결과에 따르면 lead pin의 코너부와 리드핀의 헤드부와 솔더의 경계면이 국부적으로 응력이 집중되는 가장 취약한 위치이며 lead pin의 열처리 온도가 높을수록 발생하는 최대 응력과 변형률 에너지 밀도가 낮아져서 신뢰성이 우수한 것으로 판단된다. 또한 lead pin의 코너부에 라운드가공을 하면 헤드부와 솔더의 경계면에서 발생하는 von Mises 응력과 전변형률 에너지 밀도가 감소하였다. 이와 같은 해석결과는 전 변형률 에너지 밀도가 증가할수록 솔더의 피로수명이 감소하는 연구결과에 미루어볼 때 열처리를 통해 리드핀의 기계적특성을 변경하면 PGA 패키지의 신뢰성을 향상시킬 수 있음을 의미한다. 따라서, 리드핀의 형상최적화와 열처리를 통한 최적화된 소재특성을 통해 PGA 패키지의 신뢰성 향상이 요구된다.

• 항공우주시스템공학회지
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• 제18권2호
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• pp.12-20
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• 2024

초소형 위성체의 태생적 공간 제약으로 탑재 전장품은 발사진동환경 하 구조건전성 확보를 위한 보강설계 적용에 한계가 존재하며, 피로파괴에 취약한 고집적 소자의 실장으로 고신뢰도의 평가기법이 요구된다. 종래 전장품 구조건전성 평가를 위해 Steinberg 피로파괴 이론이 적용되고 있으나 최근 연구들에서 이론적 한계점들이 보고되고 있다. 본 논문에서는 상기 이론의 한계점을 극복한 임계변형률 이론기반 방법론을 적용하여 초소형 SAR 군집위성 S-STEP(Small SAR Technology Experimental Project)의 X대역 SAR 탑재체 구성품 중 DCU(Digital Control Unit)를 설계하였다. 설계 유효성 검증을 위해 단순화된 모델링 기법을 기반으로 모드 해석, 랜덤 해석을 수행하였다. 적용한 방법론을 기반으로 해석 결과분석 및 안전여유 도출과 발사진동환경시험 전후 기능시험을 통해 최종적으로 전장품의 구조건전성이 확보됨을 입증하였다.

• 항공우주시스템공학회지
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• 제12권4호
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• pp.98-105
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• 2018

위성에 탑재되는 전장품의 경우 발사 진동환경에 대한 신뢰성 확보가 필수적이기 때문에 인증모델 제작 전 박스 레벨에서 설계요구조건에 대한 해석적 검증이 요구된다. 또한, 위성 전장품에는 다양한 실장 형태의 고집적 소자가 적용되기 때문에 솔더 접합부(Solder Joint)의 구조건전성 분석을 통한 신뢰성 확보가 필수적이다. 본 논문에서는 차세대 중형위성 광학 탑재체 제어기의 일부인 CCB(Camera Controller Box)에 대한 구조 설계 요구조건을 만족하기 위하여, 박스 레벨에서 모드 해석 및 준정적 해석을 수행하였다. 아울러, CCB 주요 소자의 안전성 분석을 위해 피로파괴 예측 이론에 기반한 구조 해석을 수행하였으며, 주요 소자 유한 요소 상세 모델 구축을 통한 랜덤 등가 정적 해석을 실시하여 전장품의 구조 건전성을 평가하였다.