• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.33-41
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• 2010

Crack propagation mechanisms of Sn-3.0Ag-0.5Cu solder were studied in strain controlled push-pull creepfatigue conditions using the fast-fast (pp) and the slow-fast (cp) strain waveforms at 313 K. Transgranular cracking was found in the pp strain waveform which led to the cycle-dominant crack propagation and intergranular cracking in the cp strain waveform that led to the time-dominant crack propagation. The time-dominant crack propagation rate was faster than the cycle-dominant crack propagation rate when compared with J-integral range which resulted from the creep damage at the crack tip in the cp strain waveform. Clear recrystallization around the crack was found in the pp and the cp strain waveforms, but the recrystallized grain size in the cp strain waveform was smaller than that in the pp strain waveform. The cycle-dominant crack propagated in the normal direction to the specimen axis macroscopically, but the time-dominant crack propagated in the shear direction which was discussed in relation with shear micro cracks formed at the crack tip.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.8
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• pp.661-669
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• 2021

A mechanical stiffener has been mainly applied on a PCB to secure fatigue life of a solder joint of an electronic components in spaceborne electronics by minimizing bending displacement of the PCB. However, it causes an increase of mass and volume of the electronics. The high damping PCB implemented by multi-layered viscoelastic tapes of a previous research was effective for assuring the fatigue life of the solder joint, but it also has a limitation to decrease accommodation efficiency for the components on the PCB. In this study, we proposed high damping PCB with a multi-layered superelastic shape memory alloy stiffener for spatialminimized, light-weighted, high-integrated structure design of the electronics. To investigate the basic characteristics of the proposed PCB, a static load test, a free vibration test were performed. Then, the high damping characteristic and the design effectiveness of the PCB were validated through a random vibration test.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.3_1spc
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• pp.504-508
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• 2013

This paper describes in detail the life prediction models and simulations of thermal fatigue under different mold compounds and chip sizes for wafer-level embedded SiP. Three-dimensional finite element models are built to simulate the viscoplastic behaviors for various mold compounds and chip sizes. In particular, the bonding parts between a mold and silicon nitride (Si3N4) are carefully modeled, and the strain distributions are studied. Three different chip sizes are used, and the effects of the mold compounds are observed. Through the numerical studies, it is found that type-C, which has a relatively lower Young's modulus and higher CTE, has a better fatigue life than the other mold compounds. In addition, the $4{\times}4$ chip has a shorter life than the $6{\times}6$ and $8{\times}8$ chips.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.147-163
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• 2003

European Union bans the usage of Pb in electronics from July 1 st, 2006. The Near-eutectic Sn-Ag-Cu alloys are the leading candidate Pb-free solders (for SMT card assembly). .The microstructure of Sn-Ag-Cu alloys is discussed in terms of solidification, composition and cooling rate. Methods of controlling Ag3Sn plates are discussed. .Thermo-mechanical fatigue behaviors of Sn-Ag-Cu solder joints are reviewed. Tin pest, whisker growth, electromigration of Pb-free solders are discussed.

• Journal of Welding and Joining
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• v.29 no.1
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• pp.46-51
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• 2011

TSV technology raises several reliability concerns particularly caused by thermally induced stress. In traditional package, the thermo-mechanical failure mostly occurs as a result of the damage in the solder joint. In TSV technology, however, the driving failure may be TSV interconnects. In this study, the thermomechanical reliability of TSV technology is investigated using finite element method. Thermal stress and thermal fatigue phenomenon caused by repetitive temperature cycling are analyzed, and possible failure locations are discussed. In particular, the effects of via size, via pitch and bonding pad on thermo-mechanical reliability are investigated. The plastic strain generally increases with via size increases. Therefore, expected thermal fatigue life also increase as the via size decreases. However, the small via shows the higher von Mises stress. This means that smaller vias are not always safe despite their longer life expectancy. Therefore careful design consideration of via size and pitch is required for reliability improvement. Also the bonding pad design is important for enhancing the reliability of TSV structure.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.1
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• pp.9-17
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• 2010

In this study, von Mises stress and total strain energy density characteristics of lead pin in PGA (Pin Grid Array) packages have been calculated by using the FEM (Finite Element Method). FEM computation is carried out with various heat treatment conditions of lead pin material under $20^{\circ}$ bending and 50 mm tension condition. Results show that von Mises stress locally concentrated on lead pin corners and interface between lead pin head and solder. von Mises stress and total strain energy density decrease as heat treatment temperature of lead pin increases. Also, round shaped corner of lead pin decreases both von Mises stress and total strain energy density on interface between lead pin head and solder. This means that PGA package reliability can be improved by changing the mechanical property of lead pin through heat treatment. This has been known that solder fatigue life decreases as total strain energy density of solder increases. Therefore, it is recommended that both optimized lead pin shape and optimized material property with high lead pin heat treatment temperature determine better PGA package reliability.

• Journal of Aerospace System Engineering
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• v.18 no.2
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• pp.12-20
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• 2024

The application of reinforcement design to ensure the structural safety of electronics in small satellites is limited by the spatial constraints of the satellite structure during launch vibrations. Additionally, a reliable evaluation approach is needed for mounting highly integrated devices that are susceptible to fatigue failure. Although the Steinberg fatigue failure theory has been used to assess the structural integrity of electronic devices, recent studies have highlighted its theoretical limitations. In this paper, we propose a structural methodology based on the critical strain theory to design the digital control unit (DCU) of the X-band SAR payload component for the small SAR technology experimental project (S-STEP), a small satellite constellation. To validate the design, we conducted modal and random analyses using simplified modeling techniques. Based on our methodology, we ultimately demonstrated the structural safety of the electronics through analysis results, safety margin derivation, and functional tests conducted both before and after the launch test.

• Journal of Aerospace System Engineering
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• v.12 no.4
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• pp.98-105
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• 2018

The satellite is exposed to various launch environments such as random vibrations and shock. Accordingly, structural design of electronic equipment mounted on satellite must meet reliability requirements at the box level. In addition, it is essential to secure the reliability of the solder joint applied to electronic equipment. In this paper, we performed a modal and quasi-static analysis for the purpose of satisfaction of the design requirements of the CCB (Camera Controller Box) present on the 500 kg-class compact advanced satellite (CAS500). In addition, structural safety of electronic components was verified by the Steinberg's method and random equivalent static analysis.