• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.103-105
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• 2003

COG (Chip on Glass) technology using solder bump reflow has been investigated to attach IC chip directly on glass substrate of LCD panel. As It chip and LCD panel have to be heated to reflow temperature of the so]der bumps for COG bonding, it is necessary to use low-temperature solders to prevent the damage of liquid crystals of LCD panel. In this study, using the Sn-52In solder bumps of $40{\mu}m$ pitch size, solder joints between Si chip and glass substrate were made at temperature below $150^{\circ}C$. The contact resistance of the solder joint was $8.58m\Omega$, which was much lower than that of the joint made using the conventional ACF bonding technique. The Sn-52In solder joints with underfill showed excellent reliability at a hot humid environment.

• 마이크로전자및패키징학회지
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• 제20권2호
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• pp.17-22
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• 2013

본 연구에서는 Sn-58Bi 솔더를 이용한 경성 인쇄 회로 기판 (Rigid printed circuit board, RPCB)과 연성 인쇄회로 기판 (Flexible printed circuit board, FPCB) 간의 열압착 접합 시, 접합 조건에 따른 기계적 특성에 대하여 연구하였다. 접합 온도와 접합 시간을 변수로 열압착 접합을 실시하여 $90^{\circ}$ 필 테스트(Peel test)를 통해 접합 강도를 측정하고, 단면과 파단면을 관찰하였다. 접합 온도가 증가할수록 접합 강도가 증가하였으며, 접합 시간에 따른 접합 강도의 변화 또한 관찰할 수 있었다. 접합 시간이 증가하면서 접합부의 파괴에 영향을 미치는 요인이 솔더 층에서 금속간 화합물(Intermetallic compound, IMC) 층으로 변화하는 것을 관찰할 수 있었다. 필 테스트 과정의 F-x(Force-distance) curve를 통해 파괴 에너지를 계산하여 금속간 화합물이 접합 강도에 미치는 영향을 평가하였으며, 본 연구에서 $195^{\circ}C$, 7초 조건이 접합 강도와 파괴 에너지가 가장 높게 나타나는 최적 접합 조건으로 도출되었다.

• 한국정밀공학회지
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• 제29권5호
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• pp.563-571
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• 2012

In 3D integration package using TSV technology, bonding is the core technology for stacking and interconnecting the chips or wafers. During bonding process, however, warpage and high stress are introduced, and will lead to the misalignment problem between two chips being bonded and failure of the chips. In this paper, a finite element approach is used to predict the warpages and stresses during the bonding process. In particular, in-plane deformation which directly affects the bonding misalignment is closely analyzed. Three types of bonding technology, which are Sn-Ag solder bonding, Cu-Cu direct bonding and SiO2 direct bonding, are compared. Numerical analysis indicates that warpage and stress are accumulated and become larger for each bonding step. In-plane deformation is much larger than out-of-plane deformation during bonding process. Cu-Cu bonding shows the largest warpage, while SiO2 direct bonding shows the smallest warpage. For stress, Sn-Ag solder bonding shows the largest stress, while Cu-Cu bonding shows the smallest. The stress is mainly concentrated at the interface between the via hole and silicon chip or via hole and bonding area. Misalignment induced during Cu-Cu and Sn-Ag solder bonding is equal to or larger than the size of via diameter, therefore should be reduced by lowering bonding temperature and proper selection of package materials.

• Journal of Welding and Joining
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• 제19권3호
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• pp.311-316
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• 2001

This paper presents that the affecting factors to the solderability and initial reliability. It is the factor that the coefficient of thermal expansion between package and PCB(Printed Circuit Board), the quantity of solder paste and reflow condition, and Au thickness of the solder ball pad on polyimide tape. As the reflow soldering condition for 48 ${\mu}BGA$ is changed, it is estimated that the quantity of Au diffusion at eutectic Sn-Pb solder surface and initial bonding strength of eutectic Sn-Pb solder and lead free solder. It is the result that quantitative measurement of Au diffusion quantity is difficult, but the shear strength of eutectic Sn-Pb solder joint is 842 mN at first reflow and increases 879 mN at third reflow. The major failure mode in solder is judged solder fracture. So, Au diffusion quantity is more affected by reflow temperature than by the reflow times.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.138-140
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• 2001

Fluxless flip chip bonding using plasma & ultrasonic wave was investigated in order to evaluate the effect of plasma & ultrasonic treatment on the bondability of the Sn-3.5wt%Ag solder bumped die to TSM-coated glass substrate. The $Ar+10%H_2plasma$ was effective in removing tin oxide on solder surface. The die shear strength of the plasma-treated Si-chip is higher than that of non-treated specimen but lower than that of specimen bonded with flux. The die shear strength with the bonding load at 25W ultrasonic power increased to 0.8N/bump for all bonding temperature but decreased above 1.0N/bump.

• 마이크로전자및패키징학회지
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• 제14권2호
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• pp.49-57
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• 2007

본 연구에서는 Au 와 Sn을 rf-magnetron sputter를 이용하여 다층막(multilayer)과 동시증착(Co-sputter)방법으로 스퍼터링하여 기판위에 AuSn 솔더를 형성하였고, 솔더의 조성제어와 특성 분석을 통해 Sn rich AuSn 솔더의 형성 기술에 대하여 연구하였다. AuSn 솔더를 형성하기 앞서 Au와 Sn에 대하여 단일 금속 증착을 하였다. 이를 토대로 AuSn솔더를 증착하기 위한 실험 조건을 확보하였다. 증착변수로는 기판의 온도, rf 전력과 두께 비를 이용하였다. 다층막의 경우, 고온의 기판에서 솔더 합금의 표면거칠기와 조성이 보다 정확하게 제어되었다. 이에 비해 동시증착 솔더는 기판의 온도에 의한 조성의 변화가 거의 없었으나, rf전력에 의해서 조성이 보다 쉽게 제어할 수 있었다. 여기에 더해, 동시 증착 솔더 박막의 대부분은 증착동안에 금속간 화합물로 변화한 것을 알 수 있었다. 화합물의 종류는 XRD로 분석하였다. 형성된 솔더 박막을 플럭스를 이용하지 않고 리드프레임에 접합하여 접합강도를 측정하였다. 다층형의 경우 Au 10wt%의 조건에서 최대 $33(N/mm^2)$ 전단응력을 나타내었으며, 동시증착형은 Au 5wt%에서 $460(N/mm^2)$ 전단응력을 나타내었다.

• 한국전기전자재료학회논문지
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• 제29권3호
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• pp.152-158
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• 2016

The bonding characteristics of MLCCs (multi layer ceramic capacitor, C1608) lead-free solder (SAC305) joints were evaluated through thermal shock test ($-40^{\circ}C{\sim}125^{\circ}C$, total 1,800 cycle). After the test, IMCs( intermetallic compounds) growth and cracks were verified, also shear strengths were measured for degradation of solder joints. In addition, The thermal stress distributions at solder joints were analyzed to compare the solder joints changes before and after according to thermal shock test by FEA (finite elements analysis). We considered the effects of IMCs growth at solder joints. As results, the bonding characteristics degradation was occurred according to initial crack, crack propagations and thermal stress concentration at solder-IMCs interface, when the IMCs grown to solder inside.

• Journal of Welding and Joining
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• 제23권3호
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• pp.61-67
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• 2005

Since lead (Pb)-free solders for electronics have higher melting points than that of eutectic Sn-Pb solder, they need higher soldering temperatures. In order to decrease the soldering temperature we tried to coat Sn-Bi layer on $Sn-3.5\%Ag$ solder by electroplating, which applies the mechanism of transient liquid phase bonding to soldering. During heating Bi will diffuse into the $Sn-3.5\%Ag$ solder and this results in decreasing soldering temperature. As bonding samples, the 1608 capacitor electroplated with Sn, and PCB, its surface was finished with electroless-plated Ni/Au, were selected. The $Sn-95.7\%Bi$ coated Sn-3.5Ag was supplied as a solder between the capacitor and PCB land. The samples were reflowed at $220^{\circ}C$, which was lower than that of normal reflow temperature, $240\~250^{\circ}C$, for the Pb-free. As experimental result, the joint of $Sn-95.7\%Bi$ coated Sn-3.5Ag showed high shear strength. In the as-reflowed state, the shear strength of the coated solder showed 58.8N, whereas those of commercial ones were 37.2N (Sn-37Pb), 31.4N (Sn-3Ag-0.5Cu), and 40.2N (Sn-8Zn-3Bi). After thermal shock of 1000 cycles between $-40^{\circ}C$ and $+125^{\circ}C$, shear strength of the coated solder showed 56.8N, whereas the previous commercial solders were in the range of 32.3N and 45.1N. As the microstructures, in the solder $Ag_3Sn$ intermetallic compound (IMC), and along the bonded interface $Ni_3Sn_4$ IMC were observed.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2003년도 춘계학술발표대회 개요집
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• pp.224-227
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• 2003

The longitudinal thermosonic bonding method is investigated in this work for its application to the soldering process for electronic packaging. The effect of the ultrasonic is analyzed through lumped modeling, and the material properties of a viscoelastic model are measured experimentally. The thermosonic bonding method is verified by inserting the Cu pin and Au bump into solder block. As the solder thickness decreases, temperature of the solder is calculated to increase rapidly because of larger strain. Localized heating due to ultrasonic vibration is observed to melt the solder near the pin, which is adequate to the high density electronic package and Pb-free solder having high melting temperature.

• 한국재료학회지
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• 제17권3호
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• pp.152-159
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• 2007

When the electronics are tested with thermal shock for Pb-free solder joint reliability, there are temperature conditions with use environment but number of cycles for test don't clearly exist. To obtain the long term reliability data, electronic companies have spent the cost and times. Therefore this studies show the test method and number of thermal shock cycles for evaluating the solder joint reliability of electronic components and also research bonding strength variation with formation and growth of intermetallic compounds (IMC). SMD (surface mount device) 3216 chip resistor and 44 pin QFP (quad flat package) was utilized for experiments and each components were soldered with Sn-40Pb and Sn-3.0 Ag-0.5 Cu solder on the FR-4 PCB(printed circuit board) using by reflow soldering process. To reliability evaluation, thermal shock test was conducted between $-40^{\circ}C\;and\;+125^{\circ}C$ for 2,000 cycles, 10 minute dwell time, respectively. Also we analyzed the IMCs of solder joint using by SEM and EDX. To compare with bonding strength, resistor and QFP were tested shear strength and $45^{\circ}$ lead pull strength, respectively. From these results, optimized number of cycles was proposed with variation of bonding strength under thermal shock.