• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• Journal of IKEEE
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• v.17 no.4
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• pp.428-433
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• 2013

In this study, an 4H-SiC Trench MOS Barrier Schottky (TMBS) rectifier which utilizes the trapezoid mesa structure and the upper half of the trench sidewall is proposed to improve the forward voltage drop and reverse blocking voltage concurrently. The proposed 4H-SiC TMBS rectifier reduces the forward voltage drop by 12% compared to the conventional 4H-SiC TMBS rectifier with the tilted sidewall and improves the reverse blocking voltage by 11% with adjusting the length of the upper sidewall. The Silvaco T-CAD was used to analyze the electrical characteristics.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.48-56
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• 1989

Contact-type linear image sensors for facsimile have been fabricated by means of rf glow discharge decomposition method of silane. The dependence of their electrical and optical properties on rf power, $SiH_4$ flow rate, ambient gas pressure, $H_2SiH_4$ ratio and substrate temperature are described. The a-Si:H monolayer demonstriated photosensitivity of 0.85 and $I_{ph}/I_d$ ratio of 100 unger 100 lux illumination. However, this monolayer has relatively high dark current due to carrier injection from both electrodes, resulting in low $I_{ph}/I_{dd}$ ratio. To suppress the dark current we have fabricated $SiO_2/i-a-Si:H/p-a-Si:H:B$ multilayer film with blocking structure. The photocurrent of this multilayer sensor with 6 V bias became saturated ar about 20nA under 10 lux illumination, while the dark current was less than 0.2 nA. Moreover, the spectral sensitivity of the multilayer film was enhanced for short wavelength visible region, compared with that of the a-Si:H monolayer. These results show that the fabricated photocon-ductive film can be used as the linear image sensor of the facsimile.

• Journal of IKEEE
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• v.24 no.2
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• pp.409-418
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• 2020

In this paper, an integrated optical, evanescent-wave biosensor utilizing a multimode interferometer based on a Si₃N₄ rib-optical waveguide consisting of the Si/SiO₂/Si₃N₄/SiO₂ stacked structure was described. The theoretical background of the multimode interferometer was reviewed, and the structure and design process were presented through numerical computational analysis. We analyzed how the dimension (length, width) of the multimode interferometer affected the sensor performance. It has been confirmed through computational analysis that the changes in the refractive index of an analyte greatly affect the mode pattern formation position and output optical power of a multimode interferometer, and proved that this principle could be applied to integrated-optic biosensor.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.61-66
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• 2005

This paper describes a 10-bit 210MHz CMOS current-mode Digital-to-Analog Converter (DAC) consisting of 6 bit MSB current cell matrix Sub-DAC, 2 bit mSB unary current source Sub-DAC, and 2 bit LSB binary weighting Sub-DAC for Wireless LAN application. A new deglitch circuit is proposed to control a crossing point of signals and minimize a glitch energy. The proposed 10-bit CMOS current mode DAC was designed by a $0.35{\mu}m$ CMOS double-poly four-metal technology rate of 210MHz, DNL/INL of ${\pm}0.7LSB/{\pm}1.1LSB$, a glitch energy of $76pV{\cdot}sec$, a SNR of 50dB, a SFDR of 53dB at 200MHz sampling clock and power dissipation of 83mW at 3.3V

• Journal of Sensor Science and Technology
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• v.29 no.4
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• pp.255-260
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• 2020

In this study, we developed a method of improving the surface-enhanced Raman spectroscopy (SERS) response characteristics by depositing a nanoporous Ag metal thin film through cluster source sputtering after forming a pyramidal texture structure on the Si substrate surface. A reactive ion etching (RIE) system with a metal mesh inside the system was used to form a pyramidal texture structure on the Si surface without following a complicated photolithography process, unlike in case of the conventional RIE system. The size of the texture structure increased with the RIE process time. However, after a process time of 60 min, the size of the structure did not increase but tended to saturate. When the RF power increased from 200 to 250 W, the size of the pyramidal texture structure increased from 0.45 to 0.8 ㎛. The SERS response characteristics were measured by depositing approximately 1.5 ㎛ of nanoporous Ag metal thin film through cluster sputtering on the formed texture structure by varying the RIE process conditions. The Raman signal strength of the nanoporous Ag metal thin film deposited on the Si substrate with the texture structure was higher than that deposited on the general silicon substrate by up to 19%. The Raman response characteristics were influenced by the pyramid size and the number of pyramids per unit area but appeared to be influenced more by the number of pyramids per unit area. Therefore, further studies are required in this regard.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.49-54
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• 2009

This paper describes implementation of the 1.9GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma }-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.2{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.1{\times}0.4mm^2$. The test results show that there is no special spurs except -63.06dB of the 6MHz reference spurs in the PLL circuitry. There is good phase noise performance like -116.17dBc/Hz in 1MHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.87-93
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• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.7
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• pp.394-399
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• 2016

The silicon dioxide ($SiO_2$) was deposited using various gas as oxygen and nitrous oxide ($N_2O$) in nowadays. In order to improve electrical characteristics and the interface state density ($D_{it}$) in low temperature, It was deposited with carbon dioxide ($CO_2$) and silane ($SiH_4$) gas by inductively coupled plasma chemical vapor deposition (ICP-CVD). Each $D_{it}$ of $SiO_2$ using $CO_2$ and $N_2O$ gas was $1.30{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$ and $3.31{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$. It showed $SiO_2$ using $CO_2$ gas was about 2.55 times better than $N_2O$ gas. After 10 years when the thin film was applied to metal/insulator/semiconductor(MIS)-nonvolatile memory(NVM), MIS NVM using $SiO_2$($CO_2$) on tunneling layer had window memory of 2.16 V with 60% retention at bias voltage from +16 V to -19 V. However, MIS NVM applied $SiO_2$($N_2O$) to tunneling layer had 2.48 V with 61% retention at bias voltage from +20 V to -24 V. The results show $SiO_2$ using $CO_2$ decrease the $D_{it}$ and it improves the operating voltage.