• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.343-343
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• 2010

In this paper, Schottky barrier thin-film-transistors (SB-TFTs) with platinum silicide at source/drain region based on glass substrate were fabricated. Poly-silicon on glass substrates was crystallized by excimer laser annealing (ELA) method. The formation of pt-silicide at source/drain region is the most important process for SB-TFTs fabrication. We study the optimal condition of Pt-silicidation on glass substrate. Also, we propose this device as promising structure in the future.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.252-258
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• 2013

In this paper, a thermally stable nickel silicide technology using the co-sputtering of nickel and titanium atoms capped with TiN layer is proposed for nano-scale metal oxide semiconductor field effect transistor (MOSFET) applications. The effects of the incorporation of titanium ingredient in the co-sputtered Ni layer are characterized as a function of Ti sputtering power. The difference between the one-step rapid thermal process (RTP) and two-step RTP for the silicidation process has also been studied. It is shown that a certain proportion of titanium incorporation with two-step RTP has the best thermal stability for this structure.

• 한국결정학회지
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• 제12권3호
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• pp.166-170
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• 2001

실리콘 기판에 도핑되어 있는 도판트는 종류에 따라 코발트와 실리콘 기판과의 반응에 영향을 준다. 인은 붕소나 비소에 비해 코발트와 실리콘과의 반응을 억제하여 저온 열처리 동안에 CoSi₂대신에 CoSi가 형성되도록 한다. CoSi층 내에서의 확산원소는 Si으로, CoSi 층은 Co/CoSi 계면에서 성장하며 반응에 참여하는Si 소모에 의해 생기는 기판의 빈 공간을 태우기 위해 Si 기판쪽으로 이동한다. 게이트 측벽에서는 접촉되어 있는 게이트 산화막과의 결합에 의해 CoSi층의 이동이 억제된다. 따라서 기판의 빈 공간을 태우지 못하게 되어 게이트 측벽 아래에 기공이 형성된다.

• Transactions on Electrical and Electronic Materials
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• 제5권5호
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• pp.180-184
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• 2004

This paper proposes a novel methodology of systematic global calibration and validates its accuracy and efficiency with application to memory and logic devices. With 175 SIMS profiles which cover the range of conditions of implant and diffusion processes in the fabrication lines, the dominant diffusion phenomenon in each process temperature region has been determined. Using the dual-pearson implant model and fully-coupled diffusion model, the calibration was performed systematically. We applied the globally calibrated process simulator parameters to memory and logic devices to predict the optimum process conditions for target device characteristics.

• Transactions on Electrical and Electronic Materials
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• 제16권4호
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• E2M - 전기 전자와 첨단 소재
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• 제4권4호
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• pp.304-311
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• 1991

본 연구에서는 p형(100) 실리콘 기판 위에 LPCVD법으로 산화막과 다결정 실리콘을 증착하고 그 위에 Magnetron Sputtering법으로 티타늄을 500.angs.을 증착한 후, 열처리 온도 500-900.deg.C 사이에서 열처리 시간을 변화시키면서 N$_{2}$ 분위기 속에서 급속 열처리하여 티타늄 실리사이드를 형성하고 그 특성을 조사하였다. 500-600.deg.C 온도 범위에서 10초간 열처리한 시료에서는 실리사이드상은 나타나지 않고, 산소등의 불순물이 티타늄 박막 내로 확산되어 600.deg.C에서 면 저항이 최대값을 보였으며 열처리 온도는 675-750.deg.C로 높이자 TiSi상이 나타나면서 면저항이 감소되고 결정립의 크기가 크게 증가하였다. 또한 열처리온도 800.deg.C에서 나타나기 시작한 TiSi$_{2}$상은 열처리 온도 850.deg.C까지 TiSi상과 공존하면서 면저항과 reflectance는 계속 감소했다. 900.deg.C에서 10초간 열처리한 시료에서는 orthorhombic구조의 완전한 실리사이드 상만 나타났다. 최종적인 티타늄 실리사이드 박막의 두께는 1200.angs.이며 비저항은 18.mu..OMEGA.cm였다.

• 반도체디스플레이기술학회지
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• 제6권3호
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• pp.19-23
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• 2007

The NiSi is very promising candidate for the metallization in 45 nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25\;{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5\;{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process temperature window for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5\;{\Omega}/{\square}$ and $3\;{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• 한국재료학회지
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• 제8권4호
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• pp.288-292
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• 1998

n-well Si(100) 영역에 $BF_{2}$를 이온주입 [에너지: 30KeV, 주입량 : $5\times10^{15}cm^{-2}$] 하고 Co($120\AA$)/Ti($40\AA$)이중막을 진공증착하여 RTA-silicidation을 통해 Co/Ti 이중막 실리사이드층을 갖는 p+ -n극저접합 다이오드를 제작하였다. 제작된 소자의 이상계수와 비접촉저항 및 누설전류는 각각 1.06, $1.2\times10^{-6}\Omega\cdot\textrm{cm}^2$, $8.6\muA/\textrm{cm}^2$(-3V)로 나타났으며 실리사이드층을 갖는 이미터 영역의 면저항은 약 $8\Omega\Box$로, 실리상이드/실리콘 계면에서 보론 농도는 약 $6\times10^{19}cm^{-3}$으로, 실리사이드 두께(~$500\AA$)를 포함한 접합깊이는 약 $0.14\mu{m}$로 형성되었다. 다이오드 제작에서 Co/Ti 이중막 실리사이드 층의 형성은 소자의 누설전류를 다소 증가시켰으나 이상계수의 개선과 이미터 영역의 면저항 및 비접촉저항의 감소를 가져왔다.

• 대한금속재료학회지
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• 제46권11호
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• 한국재료학회지
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• 제15권5호
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• pp.301-305
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• 2005

We fabricated nickel silicide layers on whole non-patterned wafers from $p-Si(100)SiO_2(200nm)$/poly-Si(70 nm)mn(40 nm) structure by 40 sec rapid thermal annealing of $500\~900^{\circ}C$. The sheet resistance, cross-sectional microstructure, surface roughness, and phase analysis were investigated by a four point probe, a field emission scanning electron microscope, a scanning probe microscope, and an X-ray diffractometer, respectively. Sheet resistance was as small as $7\Omega/sq$. even at the elevated temperature of $900^{\circ}C$. The silicide thickness and surface roughness increased as silicidation temperature increased. We confirmed the nickel silicides iron thin nickel/poly-silicon structures would be a mixture of NiSi and $NiSi_2$ even at the $NiSi_2$ stable temperature region.