• Korean Journal of Materials Research
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• v.16 no.9
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• pp.564-570
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• 2006

Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.1000-1004
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• 2006

In this paper, thermal stability of Ni-silicide formed on the SOI substrate with $B_{11}$ has been characterized. The sheet resistance of Ni-silicide on un-doped SOI and $B_{11}$ implanted bulk substrate was increased after the post-silicidation annealing at $700^{\circ}C$ for 30 min. However, in case of $B_{11}$ implanted SOI substrate, the sheet resistance showed stable characteristics after the post-silicidation annealing up to $700^{\circ}C$ for 30 min. The main reason of the excellent property of $B_{11}$ sample is believed to be the retardation of Ni diffusion by the boron and bottom oxide layer of SOI. Therefore, retardation of Ni diffusion is highly desirable lot high performance Ni silicide technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.11
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• pp.1149-1155
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• 2004

In this paper, novel methods for improvement of thermal stability of Ni-germano Silicide were proposed for nano CMOS applications. It was shown that there happened agglomeration and abnormal oxidation in case of Ni-germano Silicide using Ni only structure. Therefore, 4 kinds of tri-layer structure, such as, Ti/Ni/TiN, Ni/Ti/TiN, Co/Ni/TiN and Ni/Co/TiN were proposed utilizing Co and Ti interlayer to improve thermal stability of Ni-germano Silicide. Ti/Ni/TiN structure showed the best improvement of thermal stability and suppression of abnormal oxidation although all kinds of structures showed improvement of sheet resistance. That is, Ti/Ni/TiN structure showed only 11 ohm/sq. in spite of 600 $^{\circ}C$, 30 min post silicidation annealing while Ni-only structure show 42 ohm/sq. Therefore, Ti/Ni/TiN structure is highly promising for nano-scale CMOS technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.24-25
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• 2006

In this study, Ni silicide on the SOI substrate doped B11 is proposed to improve thermal stability. The sheet resistance of Ni-silicide utilizing pure SOI substrate increased after the post-silicidation annealing at $600^{\circ}C$ for 30 min. However, using the proposed B11 implanted substrate, the sheet resistance showed stable characteristics after the post-silicidation annealing up to $700^{\circ}C$ for 30 min.

• Korean Journal of Materials Research
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• v.16 no.10
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• pp.656-662
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• 2006

We fabricated thermal evaporated 10 nm-$Ni_xCo_{1-x}$ (x=0.2, 0.5 and 0.8) /(poly)Si films to form nanothick cobalt nickel composite silicides by a rapid thermal annealing at $700{\sim}1100^{\circ}C$ for 40 seconds. A field emission scanning electron microscope and a micro-Raman spectrometer were employed for microstructure and silicon residual stress characterization, respectively. We observed self-aligned micro-pinholes on single crystal silicon substrates silicidized at $1100^{\circ}C$. Raman silicon peak shift indicates that the residual tensile strain of $10^{-3}$ in single crystal silicon substrates existed after the silicide process. We propose thermal stress from silicide exothermic reaction and high temperature silicidation annealing may cause the pinholes. Those pinholes are expected to be avoided by lowering the silicidation temperature. Our results imply that we may use our newly proposed composite silicides to induce the appropriate strained layer in silicion substrates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.25-34
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• 2002

In this paper, silicidation induced Schottky contact area was obtained using the current voltage(I-V) characteristics of shallow cobalt silicided p+-n and n+-p junctions. In reverse bias region, Poole-Frenkel barrier lowering influenced predominantly the reverse leakage current, masking thereby the effect of Schottky contact formation. However, Schottky contact was conclusively shown to be the root cause of the modified I-V behavior of n+-p junction in the forward bias region. The increase of leakage current in silicided n+-p diodes is consistent with the formation of Schottky contact via cobalt slicide penetrating into the p-substrate or near to the junction area and generating trap sites. The increase of reverse leakage current is proven to be attributed to the penetration of silicide into depletion region in case of the perimeter intensive n+-p junction. In case of the area intensive n+-p junction, the silicide penetrated near to the depletion region. There is no formation of Schottky contact in case of the p+-n junction where no increase in the leakage current is monitored. The Schottky contact amounting to less than 0.01% of the total junction was extracted by simultaneous characterization of forward and reverse characteristics of silicided n+-p diode.

• Korean Journal of Materials Research
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• v.8 no.3
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• pp.189-194
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• 1998

The redistribution behavior of boron during Co silicidation annealing in the Co/metal/Si system was investigated using SIMS. Ti, Nb and Hf films were used as epitaxy promoting metal layers. After annealing treatment the boron peak height was about 1 order lowered in Co/Ti/Si and Co/Nb/Si systems but the relative peak position from the surface did not change. The distribution of boron was very similar to those of Ti and Nb, because of the strong affinities of boron with them. Also, the position of the main boron peak in the Co/Hf/Si system was almost the same as that of Hf, but the distribution feature of the Co/Hf/Si system somewhat differed from those of Co/Ti/Si and Co/Nb/Si systems. This implies that the affinity between B and Hf is weaker than those of B-Ti and B-Nb. Boron tends to be depleted at the silicidelsi interface while it tends to be piled-up at the Co-metal/Co silicide interface during silicidation annealing.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.75.2-75.2
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2008.08a
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• pp.157-157
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• 2008

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.391-394
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• 2004

In this study, highly thermal stable Ni Germanosilicide has been utilized using NiPt alloy and novel NiPt/Co/TiN tri-layer. And, the Ni Germanosilicide Properties were characterized according to different Ge ratio (x) in $Si_{l-x}Ge_x$ for the next generation CMOS application. The sheet resistance of Ni Germanosilicide utilizing pure-Ni increased dramatically after the post-silicidation annealing at $600^{\circ}C$ for 30 min. Moreover, more degradation was found as the Ge fraction increases. However, using the proposed NiPt/Co/TiN tri-layer, low temperature silicidation and wide range of RTP process window were achieved as well as the improvement of the thermal stability according to different Ge fractions by the subsequent Co and TiN capping layer above NiPt on the $Si_{l-x}Ge_x$. Therefore, highly thermal immune Ni Germanosilicide up to $600^{\circ}C$ for 30 min is utilized using the NiPt/Co/TiN tri-layer promising for future SiGe based ULSI technology.