• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.507-508
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• 2006

High performance delta-sigma modulator is developed for audio-codec applications(i.e.. 16-bit resolution at a 20kHz signal bandwidth). The modulator is realized with fully-differential switched capacitor integrators. All stages employ a single-stage folded-cascode amplifier. The presented delta-sigma modulator when clocked at 3.2MHz achieves 85.2dB peak-SNDR and 94.8dB SNR. This modulator is designed in a SAMSUNG $0.18{\mu}m$ CMOS process. Finally, this paper shows the test setup and FFT result gained from delta-sigma modulator chip designed for audio applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• Bulletin of the Korean Mathematical Society
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• v.47 no.2
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• pp.385-399
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• 2010

Let $\sigma$ be an endomorphism and I a $\sigma$-ideal of a ring R. Pearson and Stephenson called I a $\sigma$-semiprime ideal if whenever A is an ideal of R and m is an integer such that $A{\sigma}^t(A)\;{\subseteq}\;I$ for all $t\;{\geq}\;m$, then $A\;{\subseteq}\;I$, where $\sigma$ is an automorphism, and Hong et al. called I a $\sigma$-rigid ideal if $a{\sigma}(a)\;{\in}\;I$ implies a $a\;{\in}\;I$ for $a\;{\in}\;R$. Notice that R is called a $\sigma$-semiprime ring (resp., a $\sigma$-rigid ring) if the zero ideal of R is a $\sigma$-semiprime ideal (resp., a $\sigma$-rigid ideal). Every $\sigma$-rigid ideal is a $\sigma$-semiprime ideal for an automorphism $\sigma$, but the converse does not hold, in general. We, in this paper, introduce the quasi $\sigma$-rigidness of ideals and rings for an automorphism $\sigma$ which is in between the $\sigma$-rigidness and the $\sigma$-semiprimeness, and study their related properties. A number of connections between the quasi $\sigma$-rigidness of a ring R and one of the Ore extension $R[x;\;{\sigma},\;{\delta}]$ of R are also investigated. In particular, R is a (principally) quasi-Baer ring if and only if $R[x;\;{\sigma},\;{\delta}]$ is a (principally) quasi-Baer ring, when R is a quasi $\sigma$-rigid ring.

• Bulletin of the Korean Mathematical Society
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• v.52 no.3
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• pp.907-914
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• 2015

In this paper, we consider a viscoelastic plate equation with p-Laplacian $u^{{\prime}{\prime}}+{\Delta}^2u-div({\mid}{\nabla}u{\mid}^{p-2}{\nabla}u)+{\sigma}(t){\int}_{0}^{t}g(t-s){\Delta}u(s)ds-{\Delta}u^{\prime}=0$. By introducing suitable energy and Lyapunov functionals, we establish a general decay estimate for the energy, which depends on the behavior of both ${\sigma}$ and g.

• Kyungpook Mathematical Journal
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• v.46 no.4
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• pp.477-488
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• 2006

In this paper, the authors first classify all nonoscillatory solutions of equation (1) $${\Delta}^2|{\Delta}^2{_{y_n}}|^{{\alpha}-1}{\Delta}^2{_{y_n}}+q_n|y_{{\sigma}(n)}|^{{\beta}-1}y_{{\sigma}(n)}=o,\;n{\in}\mathbb{N}$$ into six disjoint classes according to their asymptotic behavior, and then they obtain necessary and sufficient conditions for the existence of solutions in these classes. Examples are inserted to illustrate the results.

• Journal of the Korean Geotechnical Society
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• v.15 no.3
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• pp.151-160
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• 1999

The settlement limit concept is generally adopted as design criteria of rock-socketed pile foundations, therefore, the load-displacement$(\sigma-\sigma)$ behavior of the rock-socketed piles should be well understood at the design stage, which, however, is hard to achieve due to its complexity. To help this out, field pile load tests are executed on cast-in-situ concrete piles, first, to figure out the $\sigma$-$\delta$ behavior of rock-socketed piles. Next, the $\sigma-\sigma$ relations of the piles are simulated numerically using commercial package program(ELAC) varying a couple of input data which are sensitive in shaping the $\sigma$-$\delta$ curves. Finally, the relation between the best input data for the numerical simulations and the geotechnical field data are cultivated to generalize the numerical simulation procedures, which enables geotechnical engineers to predict the $\sigma$-$\delta$ behavior at the design stage, if appropriate geotechnical field data are provided.

• Journal of the Earthquake Engineering Society of Korea
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• v.5 no.4
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• pp.17-26
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• 2001

In order to estimate peak ground motions and frequency characteristics of strong ground motions in southern korea, we employed the stochastic simulation method with the moment magnitude(M$_{w}$) and the hypocentral distance(R). We estimated same input parameters that account for specific properties of source and propagation processes, and applied them to the stochastic simulation method. The stress drop($\Delta$$\sigma$) of 100-bar was estimated considering results of research in ENA, China, and southern korea. The attenuation parameter x was calculated by analyzing 57 seismograms recorded from September 1996 to October 1997 and the estimation result of the attenuation parameter x is 0.00112+0.000224 R where R is hypocenter distance. We estimated strong ground motion relations using the stochastic simulation method with suitable input parameters(e.g. $\Delta$$\sigma$, x, and so on). At last, we derived relations between hypocentral distances and ground motions(seismic attenuation equation) using results of the stochastic prediction.esults of the stochastic prediction.n.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.53-58
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• 2008

This paper designs sigma-delta D/A Converter with a high resolution and low power consumption. It reorganizes the input data along LJ, RJ, I2S mode and bit mode to the output data of A/D converter. The D/A converter decodes the original analog signal through HBF, Hold and 5th CIFB(Cascaded Integrators with distributed Feedback as well as distributed input coupling) sigma-delta modulation blocks. It uses repeatedly the addition operation in instead of the multiply operation for the chip area and the performance. Also, the half band filters of similar architecture composed the one block and it used the sample-hold block instead of the sinc filter. We supposed simple D/A Converter decreased in area. The filters of the block analyzed using the matlab tool. The top block designed using the top-down method by verilog language. The designed block is fabricated using Samsung 0.35um CMOS standard cell library. The chip area is 1500*1500um.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

• Journal of IKEEE
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• v.17 no.3
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• pp.234-240
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• 2013

This paper presents an incremental delta-sigma analog-to-digital converter (ADC) for a single-electrode capacitive touch sensor. The second-order cascade of integrators with distributed feedback (CIFB) delta-sigma modulator with 1-bit quantization was fabricated by a $0.18-{\mu}m$ CMOS process. In order to achieve a wide input range in this incremental delta-sigma analog-to-digital converter, the shielding signal and the digitally controlled offset capacitors are used in front of a converter. This circuit operated at a supply voltage of 2.6 V to 3.7 V, and is suitable for single-electrode capacitive touch sensor for ${\pm}10-pF$ input range with sub-fF resolution.