• Journal of the Korean Mathematical Society
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• v.51 no.6
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• pp.1251-1267
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• 2014

The semicommutative property of rings was introduced initially by Bell, and has done important roles in noncommutative ring theory. This concept was generalized to one of nil-semicommutative by Chen. We first study some basic properties of nil-semicommutative rings. We next investigate the structure of Ore extensions when upper nilradicals are ${\sigma}$-rigid ${\delta}$-ideals, examining the nil-semicommutative ring property of Ore extensions and skew power series rings, where ${\sigma}$ is a ring endomorphism and ${\delta}$ is a ${\sigma}$-derivation.

• Proceedings of the Korean Geotechical Society Conference
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• 2010.03a
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• pp.1458-1465
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• 2010

A lot of dredging and reclaming projects are recently under way in Korea for the efficient use of limiting land space. Saemanguem area is special case of reclaiming by dredged soil. In case of a confined disposal of dredged soils by a pump dredger, generally coarse grained soils are separated from fines with dropping at the near part of the pump dredger. This kind of seperation of fine contents could be a factor of liquefaction by earthquake. In Korea, recently, earthquakes with magnitude of 3.0 or higher are distinctively increasing in 1990. In this study, cyclic shear characterics of Saemanguem Dredged sand depending on fine content were analyzed. A series of undrained cyclic triaxial test with cyclic stress ratio ($\sigma_d/{2\sigma_{{\upsilon}c}}'$) were performed on both isotropic consolidated specimen and sand with fine contents of 0%, 5%, 15%, 30%, 40% under the effective vertical stress of 100kPa and 50% and 60%, 70% of relative density for fine content of 0%, respectively. In the test results, cyclic shear strength increased by increasing of cyclic stress ratio($\sigma_d/{2\sigma_{{\upsilon}c}}'$) with increasing the relative density at the same number of cyclic under the effective confining pressure of 100kPa. It is almost highest the double amplitude(DA) 1%, 3%, 5%, 7.5% and 10% at fine content of 15% between Cyclic stress ratio($\sigma_d/{2\sigma_{{\upsilon}c}}'$) value at cyclic number five and fine content. Number of cyclic is 30 under the effective vertical stress of 100kPa, 70% of relative density for fine content of 15%. when the cyclic stress ratio at each relative density was compared at cyclic number five, the double amplitude(DA) 1%, 3%, 5%, 7.5% and 10%, and the pore-pressure ratio (${\Delta}u/{\sigma'}_c$) 0.95 value were compared; under the relative density of 70% and the effective confining pressure of 100kPa. The pore-pressure ratio (${\Delta}u/{\sigma'}_c$) 0.95 value showed a similar trend to the double amplitude (DA) 5% line.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.28 no.2C
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• pp.117-123
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• 2008

Disturbed and undisturbed decomposed granite soils with different weathering degrees were extracted and analyzed through a series of tests (CD test, constant P test, etc.) to assess their dilatancy characteristics. Here, dilatancy refers to the volume change that takes place during shearing. As a result, the decomposed granite soil dilatancy impact increased the mean effective stress while concurrently lowering the water content in drained shear tests. In the case of undisturbed decomposed granite soil, which has a lower weathering degree, the water content increased at specific limits during the shearing process. A linear relationship of ${\Delta}V_d/V_1=D{\cdot}(({\sigma}_1-{\sigma}_3)-{\sigma}_c)/{{\sigma}_m}^{\prime}$ forms between shearing-induced volume change and principal stress variance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.104-110
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• 2006

The advantage of the DSM which employ multi-bit quantizer is the increased SNR at the modulator's output. Typically 6 dB improvement is effected for every one additional bit. But multi-bit quantizer evidently requires multi-bit DAC in the feedback loop. The integral linearity error of the feedback DAC has direct impact upon the system performance and degraded SNR of the system. In order to mitigate the negative impact the DAC has on the system performance, many DEM(Dynamic Element Matching) schemes has been proposed. Among the proposed schemes, four schemes(DER,CLA,ILA,DWA) are explained and its performance has been compared. DWA(Data Weighted Averaging) method shows the best performance of the all.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.1 s.307
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• pp.39-44
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• 2006

Pattern noise in the Delta-Sigma modulator is a well Known phenomenon that intrigued many circuit designers. These noise appear as the modulator output falls into a cyclic mode of operation. This paper addresses the dependence of these tone signal upon the system topologies. Among the four well known single-stage DSM topologies, namely Cascade of Integrators with Feedback Form(CIFB), Cascade of Integrators with Feedforward Form(CIFF), Cascade of Resonators with Feedback Form(CRFB), and Cascade of Resonators with Feedforward Form(CRFF), resonator type DSMs turn out to be more susceptible to the pattern noise than the integrator type. Noise transfer functions of the investigated topologies are also presented.

• Journal of IKEEE
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• v.17 no.4
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• pp.511-516
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• 2013

This paper presents a SDM using the FDPA technique. The FDPA technique is the added feedback path which is the delayed path of DAC output. The designed SDM increases the SNR by adding the delayed digital feedback path. The proposed SDM is easily implemented by eliminating the analog feedback path. Through the MATLAB modeling, the optimized coefficients are obtained to design the SDM. The designed SDM has a power consumption of $220{\mu}W$ and SNR(signal to noise ratio) of 81dB at the signal-bandwidth of 20KHz and sampling frequency of 2.56MHz. The SDM is designed using the $0.18{\mu}m$ standard CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.25-33
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• 2007

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.

• ETRI Journal
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• v.36 no.6
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• pp.924-930
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• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.342-348
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• 2015

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.