JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

  • Lee, Jong Mi (Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) ;
  • Jee, Dong-Woo (Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) ;
  • Kim, Byungsub (Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) ;
  • Park, Hong-June (Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) ;
  • Sim, Jae-Yoon (Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH))
  • Received : 2014.10.21
  • Accepted : 2014.12.24
  • Published : 2015.06.30
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Abstract

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

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References

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