• Title/Summary/Keyword: Si through-via

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Study of SI Characteristic of Multilayer PCB with a Through-Hole Via (관통형 비아가 있는 다층 PCB의 SI 성능 연구)

  • Kim, Li-Jin;Lee, Jae-Hyun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.2
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    • pp.188-193
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    • 2010
  • In this paper, SI(Signal Integrity) characteristic of the 4-layer PCB(Printed Circuit Boards) with a through-hole via was analyzed by impedance mismatching between the through-hole via and the transmission line, and deterioration of clock pulse response characteristic due to the P/G plane resonances which are generated between the power and the ground plane. The minimized impedance mismatching between the through-hole via and the transmission line for the improving of SI characteristic is confirmed by the TDR(Time Domain Reflector) simulation and lumped element modeling of the through-hole via. And the cancellation method of P/G plane resonances for improvement of the SI characteristic is represented by simulation result.

The Effects of Current Types on Through Via Hole Filling for 3D-SiP Application (전류인가 방법이 3D-SiP용 Through Via Hole의 Filling에 미치는 영향)

  • Chang, Gun-Ho;Lee, Jae-Ho
    • Journal of the Microelectronics and Packaging Society
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    • v.13 no.4
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    • pp.45-50
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    • 2006
  • Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

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Anisotropic Wet-Etching Process of Si Substrate for Formation of Thermal Vias in High-Power LED Packages (고출력 LED 패키지의 Thermal Via 형성을 위한 Si 기판의 이방성 습식식각 공정)

  • Yu, B.K.;Kim, M.Y.;Oh, T.S.
    • Journal of the Microelectronics and Packaging Society
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    • v.19 no.4
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    • pp.51-56
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    • 2012
  • In order to fabricate through-Si-vias for thermal vias by using wet etching process, anisotropic etching behavior of Si substrate was investigated as functions of concentration and temperature of TMAH solution in this study. The etching rate of 5 wt%, 10 wt%, and 25 wt% TMAH solutions, of which temperature was maintained at $80^{\circ}C$, was $0.76{\mu}m/min$, $0.75{\mu}m/min$, and $0.30{\mu}m/min$, respectively. With changing the temperature of 10 wt% TMAH solution to $20^{\circ}C$ and $50^{\circ}C$, the etching rate was reduced to $0.067{\mu}m/min$ and $0.233{\mu}m/min$, respectively. Through-Si-vias of $500{\mu}m$-depth could be fabricated by etching a Si substrate for 5 hours in 10 wt% TMAH solution at $80^{\circ}C$ after forming same via-pattern on each side of the Si substrate.

Cu Filling process of Through-Si-Via(TSV) with Single Additive (단일 첨가액을 이용한 Cu Through-Si-Via(TSV) 충진 공정 연구)

  • Jin, Sang-Hyeon;Lee, Jin-Hyeon;Yu, Bong-Yeong
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2016.11a
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    • pp.128-128
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    • 2016
  • Cu 배선폭 미세화 기술은 반도체 디바이스의 성능 향상을 위한 핵심 기술이다. 현재 배선 기술은 lithography, deposition, planarization등 종합적인 공정 기술의 발전에 따라 10x nm scale까지 감소하였다. 하지만 지속적인 feature size 감소를 위하여 요구되는 높은 공정 기술 및 비용과 배선폭 미세화로 인한 재료의 물리적 한계로 인하여 배선폭 미세화를 통한 성능의 향상에는 한계가 있다. 배선폭 미세화를 통한 2차원적인 집적도 향상과는 별개로 chip들의 3차원 적층을 통하여 반도체 디바이스의 성능 향상이 가능하다. 칩들의 3차원 적층을 위해서는 별도의 3차원 배선 기술이 요구되는데, TSV(through-Si-via)방식은 Si기판을 관통하는 via를 통하여 chip간의 전기신호 교환이 최단거리에서 이루어지는 가장 진보된 형태의 3차원 배선 기술이다. Si 기판에 $50{\mu}m$이상 깊이의 via 및 seed layer를 형성 한 후 습식전해증착법을 이용하여 Cu 배선이 이루어지는데, via 내부 Cu ion 공급 한계로 인하여 일반적인 공정으로는 void와 같은 defect가 형성되어 배선 신뢰성에 문제를 발생시킨다. 이를 해결하기 위해 각종 유기 첨가제가 사용되는데, suppressor를 사용하여 Si 기판 상층부와 via 측면벽의 Cu 증착을 억제하고, accelerator를 사용하여 via 바닥면의 Cu 성장속도를 증가시켜 bottom-up TSV filling을 유도하는 방식이 일반적이다. 이론적으로, Bottom-up TSV filling은 sample 전체에서 Cu 성장을 억제하는 suppressor가 via bottom의 강한 potential로 인하여 국부적 탈착되고 via bottom에서만 Cu가 증착되어 되어 이루어지므로, accelerator가 없이도 void-free TSV filling이 가능하다. Accelerator가 Suppressor를 치환하여 오히려 bottom-up TSV filling을 방해한다는 보고도 있었다. 본 연구에서는 유기 첨가제의 치환으로 인한 TSV filling performance 저하를 방지하고, 유기 첨가제 조성을 단순화하여 용액 관리가 용이하도록 하기 위하여 suppressor만을 이용한 TSV filling 연구를 진행하였다. 먼저, suppressor의 흡착, 탈착 특성을 이해하기 위한 연구가 진행되었고, 이를 바탕으로 suppressor만을 이용한 bottom-up Cu TSV filling이 진행되었다. 최종적으로 $60{\mu}m$ 깊이의 TSV를 1000초 내에 void-free filling하였다.

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Developing Low Cost, High Throughput Si Through Via Etching for LED Substrate (LED용 Si 기판의 저비용, 고생산성 실리콘 관통 비아 식각 공정)

  • Koo, Youngmo;Kim, GuSung;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.19 no.4
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    • pp.19-23
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    • 2012
  • Silicon substrate for light emitting diodes (LEDs) has been the tendency of LED packaging for improving power consumption and light output. In this study, a low cost and high throughput Si through via fabrication has been demonstrated using a wet etching process. Both a wet etching only process and a combination of wet etching and dry etching process were evaluated. The silicon substrate with Si through via fabricated by KOH wet etching showed a good electrical resistance (${\sim}5.5{\Omega}$) of Cu interconnection and a suitable thermal resistance (4 K/W) compared to AlN ceramic substrate.

Copper Filling to TSV (Through-Si-Via) and Simplification of Bumping Process (비아 홀(TSV)의 Cu 충전 및 범핑 공정 단순화)

  • Hong, Sung-Jun;Hong, Sung-Chul;Kim, Won-Joong;Jung, Jae-Pil
    • Journal of the Microelectronics and Packaging Society
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    • v.17 no.3
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    • pp.79-84
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    • 2010
  • Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

The Effects of Additives on the Electropolishing of Copper Through Via (구리 Through Via 전해연마에 미치는 첨가제의 영향 연구)

  • Lee, Suk-Ei;Lee, Jae-Ho
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.1
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    • pp.45-50
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    • 2008
  • The effects of electrolytes and additives on the electropolishing of 50 and $20{\mu}m$ diameter copper via were investigated to flatten 3D SiP through via. The termination time was determined with analysis of applied potential on anode and cathode to avoid excess electropolishing. Acetic acid played a role of accelerator and glycerol played a role of inhibitor in phosphoric acid electrolytes. The overplated copper on the through via was effectively electropolished in the phosphoric electrolytes with acetic acid and glycerol addition. The electropolishing was terminated at the point of abrupt change of applied potential to remove only overplated copper on the through via.

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반도체 소자의 3차원 집적에 적용되는 through-Silicon-via (TSV) 배선의 구조형성

  • Im, Yeong-Dae;Lee, Seung-Hwan;Yu, Won-Jong;Jeong, O-Jin;Kim, Sang-Cheol;Lee, Han-Chun
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2008.11a
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    • pp.21-22
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    • 2008
  • $SF_6/O_2$ 플라즈마 에칭을 통한 반도체 칩의 3차원 집적에 응용되는 through-silicon-via (TSV) 구조형성 연구를 수행하였다. Si via 형상은 $SF_6$, $O_2$의 가스 비율과 에칭이 되는 Silicon 기판의 온도에 의존함을 알수 있었다. 또한 Si via 형상에서 최소의 언더컷 (undercut) 과 측벽에칭 (local bowing) 은 black Si이 나타나는 공정조건에서 나타남을 확인하였다. 더 나아가 저온을 이용한 via 형성시 via 측벽에 형성되는 passivation layer와 mask의 성질이 저온으로 인해 high-aspect-ratio를 갖는 via를 형성할 수 있음을 알 수 있었다.

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Fabrication of Through-hole Interconnect in Si Wafer for 3D Package (3D 패키지용 관통 전극 형성에 관한 연구)

  • Kim, Dae-Gon;Kim, Jong-Woong;Ha, Sang-Su;Jung, Jae-Pil;Shin, Young-Eui;Moon, Jeong-Hoon;Jung, Seung-Boo
    • Journal of Welding and Joining
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    • v.24 no.2
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    • pp.64-70
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    • 2006
  • The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

High -Rate Laser Ablation For Through-Wafer Via Holes in SiC Substrates and GaN/AlN/SiC Templates

  • Kim, S.;Bang, B.S.;Ren, F.;d'Entremont, J.;Blumenfeld, W.;Cordock, T.;Pearton, S.J.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.3
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    • pp.217-221
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    • 2004
  • [ $CO_2$ ]laser ablation rates for bulk 4H-SiC substrates and GaN/AIN/SiC templates in the range 229-870 ${\mu}m.min^{-1}$ were obtained for pulse energies of 7.5-30 mJ over diameters of 50·500 ${\mu}m$ with a Q-switched pulse width of ${\sim}30$ nsec and a pulse frequency of 8 Hz. The laser drilling produces much higher etch rates than conventional dry plasma etching (0.2 - 1.3 ${\mu}m/min$) making this an attractive maskless option for creating through-wafer via holes in SiC or GaN/AlN/SiC templates for power metal-semiconductor field effect transistor applications. The via entry can be tapered to facilitate subsequent metallization by control of the laser power and the total residual surface contamination can be minimized in a similar fashion and with a high gas throughput to avoid redeposition. The sidewall roughness is also comparable or better than conventional via holes created by plasma etching.