• Title/Summary/Keyword: Short-channel effects

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Dependence of Drain Induced Barrier Lowering for Ratio of Channel Length vs. Thickness of Asymmetric Double Gate MOSFET (비대칭 DGMOSFET에서 채널길이와 두께 비에 따른 DIBL 의존성 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.6
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    • pp.1399-1404
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    • 2015
  • This paper analyzed the phenomenon of drain induced barrier lowering(DIBL) for the ratio of channel length vs. thickness of asymmetric double gate(DG) MOSFET. DIBL, the important secondary effect, is occurred for short channel MOSFET in which drain voltage influences on potential barrier height of source, and significantly affects on transistor characteristics such as threshold voltage movement. The series potential distribution is derived from Poisson's equation to analyze DIBL, and threshold voltage is defined by top gate voltage of asymmetric DGMOSFET in case the off current is 10-7 A/m. Since asymmetric DGMOSFET has the advantage that channel length and channel thickness can significantly minimize, and short channel effects reduce, DIBL is investigated for the ratio of channel length vs. thickness in this study. As a results, DIBL is greatly influenced by the ratio of channel length vs. thickness. We also know DIBL is greatly changed for bottom gate voltage, top/bottom gate oxide thickness and channel doping concentration.

Hot-Carrier Effects of $BF_2$ Ion-Implanted Surface-Channel LDD PMOSFET ($BF_2$ 이온 주입한 표면 채널 LDD PMOSFET의 Hot-Carrier 효과)

  • 양광선;박훈수;김봉렬
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.12
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    • pp.53-58
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    • 1991
  • Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.

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Analysis of Doping Profile Dependent Threshold Voltage for DGMOSFET Using Gaussian Function

  • Jung, Hak-Kee
    • Journal of information and communication convergence engineering
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    • v.9 no.3
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    • pp.310-314
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    • 2011
  • This paper has presented doping profile dependent threshold voltage for DGMOSFET using analytical transport model based on Gaussian function. Two dimensional analytical transport model has been derived from Poisson's equation for symmetrical Double Gate MOSFETs(DGMOSFETs). Threshold voltage roll-off is very important short channel effects(SCEs) for nano structures since it determines turn on/off of MOSFETs. Threshold voltage has to be constant with decrease of channel length, but it shows roll-off due to SCEs. This analytical transport model is used to obtain the dependence of threshold voltage on channel doping profile for DGMOSFET profiles. Also we have analyzed threshold voltage for structure of channel such as channel length and gate oxide thickness.

An Experimental Study on the Threshold Voltage and Punchthrough Voltage Reduction in Short-Channel NMOS Transistors (채널의 길이가 짧은 NMOS 트랜지스터의 Threshold 전압과 Punchthrough 전압의 감소에 관한 실험적연구)

  • Lee, Won-Sik;Im, Hyeong-Gyu;Kim, Bo-U
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.20 no.2
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    • pp.1-6
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    • 1983
  • The reduction of threshold voltage and punchthrough voltage of short channel MOS transistors has been measured experimentally with silicon gate NMOS transistors. The effects of the gate oxide thickness and substrate doping concentration on the threshold voltage and punch-through voltage have also been measured with sample devices with boron implantation and gate oxide thickness of 50 nm and 70 nm. Hot electron emission has been measured by floating gate method for the samples with 3 ${\mu}{\textrm}{m}$ channel length. It has been concluded from this measurement that hot electron emission is not significant for the channel length of 3${\mu}{\textrm}{m}$.

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A 2-D Model for the Potential Distribution and Threshold Voltage of Fully Depleted Short-Channel Ion-Implanted Silicon MESFET's

  • Jit, S.;Morarka, Saurabh;Mishra, Saurabh
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.3
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    • pp.173-181
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    • 2005
  • A new two dimensional (2-D) model for the potential distribution of fully depleted short-channel ion-implanted silicon MESFET's has been presented in this paper. The solution of the 2-D Poisson's equation has been considered as the superposition of the solutions of 1-D Poisson's equation in the lateral direction and the 2-D homogeneous Laplace equation with suitable boundary conditions. The minimum bottom potential at the interface of the depletion region due to the metal-semiconductor junction at the Schottky gate and depletion region due to the substrate-channel junction has been used to investigate the drain-induced barrier lowering (DIBL) and its effects on the threshold voltage of the device. Numerical results have been presented for the potential distribution and threshold voltage for different parameters such as the channel length, drain-source voltage, and implanted-dose and silicon film thickness.

Tunneling Current of Sub-10 nm Asymmetric Double Gate MOSFET for Channel Doping Concentration (10 nm 이하 비대칭 DGMOSFET의 채널도핑농도에 따른 터널링 전류)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.7
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    • pp.1617-1622
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    • 2015
  • This paper analyzes the ratio of tunneling current for channel doping concentration of sub-10 nm asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current in subthreshold region increases in the region of channel length of 10 nm below. Even though asymmetric DGMOSFET is developed to reduce short channel effects, the increase of tunneling current in sub-10 nm is inevitable. As the ratio of tunneling current in off current according to channel doping concentration is calculated in this study, the influence of tunneling current to occur in short channel is investigated. To obtain off current to consist of thermionic emission and tunneling current, the analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for channel doping concentration in sub-10 nm asymmetric DGMOSFET, specially with parameters of channel length, channel thickness, and top/bottom gate oxide thickness and voltage.

Analysis of Breakdown Voltages of Double Gate MOSFET Using 2D Potential Model (이차원 전위분포모델을 이용한 이중게이트 MOSFET의 항복전압 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.5
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    • pp.1196-1202
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    • 2013
  • This paper have analyzed the change of breakdown voltage for channel doping concentration and device parameters of double gate(DG) MOSFET using two dimensional potential model. The low breakdown voltage becomes the obstacle of power device operation, and breakdown voltage decreases seriously by the short channel effects derived from scaled down device in the case of DGMOSFET. The two dimensional analytical potential distribution derived from Poisson's equation have been used to analyze the breakdown voltage for device parameters such as channel length, channel thickness, gate oxide thickness and channel doping concentration. Resultly, we could observe the breakdown voltage has greatly influenced on device dimensional parameters as well as channel doping concentration, especially the shape of Gaussian function used as channel doping concentration.

Bottom Gate Voltage Dependent Threshold Voltage Roll-off of Asymmetric Double Gate MOSFET (하단게이트 전압에 따른 비대칭 이중게이트 MOSFET의 문턱전압이동 의존성)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.6
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    • pp.1422-1428
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    • 2014
  • This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

Quantum Effects in the channel of a ${\delta}$ - doped NMOSFET (${\delta}$ - 도핑 NMOSFET 채널 내에서의 양자화 효과)

  • 문현기;김현중;이찬호
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.177-180
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    • 2001
  • The quantum effects in the channel of a $\delta$ -doped NMOSFET structures are investigated by solving Schrodinger and Poisson equations self-consistently. According to the scaling of MOSFET structures, electron distributions change by the strong energy quantization. However the presence of a low-doped epitaxial region produces a reduction of the electron effective field for a given charge sheet density and therefore, improves the electron effective mobility. We also focus the quantum-induced threshold voltage shifts, low-field electron effective mobility and gate-to-channel capacitance. The reported results give indications for the fabrication of ultra short MOSFET's.

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Relation of Conduction Path and Subthreshold Swing for Doping Profile of Asymmetric Double Gate MOSFET (비대칭 DGMOSFET의 도핑분포함수에 따른 전도중심과 문턱전압이하 스윙의 관계)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.8
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    • pp.1925-1930
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    • 2014
  • This paper has analyzed the relation of conduction path and subthreshold swing for doping profile in channel of asymmetric double gate(DG) MOSFET. Since the channel size of asymmetric DGMOSFET is greatly small and number of impurity is few, the high doping channel is analyzed. The analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. The conduction path and subthreshold swing are derived from this analytical potential distribution, and those are investigated for variables of doping profile, projected range and standard projected deviation, according to the change of channel length and thickness. As a result, subthreshold swing is reduced when conduction path is approaching to top gate, and that is increased with a decrease of channel length and a increase of channel thickness due to short channel effects.