• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.84-89
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• 2002

In this paper the Viterbi decoder which is used for TCM decoding in wireless modem system under transmission of audio data for the high quality sound is designed by VHDL and implemented by FPGA. After making short explanation about TCM encoding and decoding. I show the effect of channel in computer by using encoder and decoder implemented in FOGA and the bit error rate according to change rate of ($E_b/N_0$).

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1549-1551
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• 2002

현재 게이트 길이가 100nm 이하의 MOSFET 소자를 구현할 때 가장 대두되는 문제인 short channel effect를 억제하는 방법으로 제안된 소자 중 하나가 double gate (DG) silicon-on-insulator (SOI) MOSFET이다. 그러나 DG SOI MOSFET는 두 게이트간의 align과 threshold voltage control 문제가 있다. 본 논문에서는 DG SOI MOSFET에서 이상적으로 게이트가 align된 구조와 back 게이트가 front 게이트보다 긴 non-align된 구조가 subthreshold 동작 영역에서 impact ionization에 미치는 영향에 대해 시뮬레이션을 통하여 비교 분석하였다. 그 결과 게이트가 이상적으로 align된 구조보다 back 게이트가 front 게이트보다 긴 non-align된 구조가 게이트와 드레인이 overlap된 영역에서 impact ionization이 증가하였으며 게이트가 각각 n+ 폴리실리콘과 p+ 폴리실리콘을 가진 소자에서 두 게이트가 같은 work function을 가진 소자보다 높은 impact generation rate을 가짐을 알 수 있었다.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.1819-1824
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• 2004

The common method to improve heat transfer in Nuclear fuel rod bundle is install a mixing vane in space grid. The previous split mixing vane is guides cooling water to swirl flow in sub-channel of fuel assembly. But, this swirl flow decade rapidly after mixing vane and the effect of enhancing the heat transfer vanish behind this short region. The large scale secondary vortex flow was generated by rearranging the inclined angle direction of mixing vanes to the coordinated directions. This LSVF mixing vanes generate the most strong secondary flow vortices which maintain about 35 $D_H$ after the spacer grid and the streamwise vorticity in subchannel with LSVF mixing vane sustain two times more than that in subchannel with split mixing vane. The turbulent kinetic energy and the Reynolds stresses generated by the mixing vanes have nearly same scales but maintain twice more than previous type.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.20-27
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• 2010

Modeling is essential to simulate the operation of integrated circuit (IC) before its fabrication. Seeing a large number of Metal-Oxide-Silicon Field-Effect-Transistor (MOSFET) models available, it has become important to understand them and compare them for their pros and cons. The task becomes equally difficult when the complexity of these models becomes very high. The paper reviews the mainstream models with their physical relevance and their comparisons. Major short-channel and quantum effects in the models are outlined. Emphasis is set upon the latest compact models like BSIM, MOS Models 9/11, EKV, SP etc.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.655-661
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a surrounding gate tunnel field effect transistor (TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunneling generation rate and thus we numerically extract the tunneling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.167-168
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• 2007

Design Rule이 작아짐에 따라 Transistor performance 향상을 위한 여러 방안중 SEG 공정이 적용되고 있으며 이에 따른 Transistor 특성 연구 결과이다. SEG공정 적용시 SEG Profile에 따라 Transistor의 Short Channel Effect 열화가 발생하였고 그 원인은 Sidewall Facet발생으로 추정되며 이를 개선시 Tr 특성이 개선됨을 확인하였다.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.18 no.10
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• pp.811-818
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• 2006

Mixing vanes have been installed in the space grid of nuclear fuel rod bundle to improve turbulent heat transfer. Split mixing vanes induce the vortex flow in the cooling water to swirl in sub-channel of fuel assembly. But, The swirling flow decays rapidly so that the heat transfer enhancing effect limited to short length after the mixing vane. In the present study, the large scale vortex flow (LSVF) is generated by rearranging the mixing vanes to the coordinated directions. This LSVF mixing vanes generate the most strong secondary flow vortices which maintain about $35D_h$ after the spacer grid. The streamwise vorticity generated by LSVF sustain two times more than that split mixing vane.

• ETRI Journal
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• v.44 no.3
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.