• 한국전기전자재료학회논문지
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• 제34권5호
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• pp.296-300
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• 2021

The performance of devices has been improved with fine processes from planar to three-dimensional transistors (e.g., FinFET, NWFET, and MBCFET). There are some problems such as a short channel effect or a self-heating effect occur due to the reduction of the gate-channel length by miniaturization. To solve these problems, we compare and analyze the electrical and thermal characteristics of FinFET and GAAFET devices that are currently used and expected to be further developed in the future. In addition, the optimal structure according to the Fin shape was investigated. GAAFET is a suitable device for use in a smaller scale process than the currently used, because it shows superior electrical and thermal resistance characteristics compared to FinFET. Since there are pros and cons in process difficulty and device characteristics depending on the channel formation structure of GAAFET, we expect a mass-production of fine processes over 5 nm through structural optimization is feasible.

• 문화기술의 융합
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• 제7권4호
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• pp.659-665
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• 2021

최근 폭발적인 인기를 끌고있는 짧은 동영상 애플리케이션(e.g., TikTok, YouTube Shorts)은 광고집행을 위한 새로운 SNS 플랫폼으로 관심을 받고 있다. 이러한 배경에서 본 연구는 짧은 동영상 애플리케이션에서 집행되고 있는 스토리텔링 광고를 분류하고 그 효과를 측정하는 것을 목적으로 한다. 상술 하면, 전통적 광고 분류기준인 허구성을 기준으로 스토리텔링 광고를 리얼리티, 패러디, 창의형식으로 구분하였다. 또한 인지심리학 정보처리 맥락에서 높은 수준과 낮은 수준의 메시지가치가(MSV)로 광고들을 분류하였다. 전 세계적으로 가장 많은 이용자를 보유한 틱톡을 대상으로 총 784명 중국인 이용자의 응답을 수집하였다. 연구결과 두 개의 주요 변인(허구성과 MSV) 간에 유의미한 조절효과가 발생하였다. 가장 주목할 만한 결과는 정보처리 리소스의 사용을 높게 요구하는 높은 허구성의 창의적 기법이 높은 메시지자극가를 사용하게 되면 인지과부하(cognitive overload)를 야기하여 광고효과가 낮아지는 것으로 나타났다. 보다 자세한 이론적 논의와 효과적인 짧은 동영상 스토리텔링 광고제작을 위한 제언들을 본문에서 상세히 소개하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.473-481
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• 2012

For a mesa-isolated small geometry SOI MOSFET, the potentials in the silicon film, front, back, and side-wall oxide layers can be derived three-dimensionally. Using Taylor's series expansions of the trigonometric functions, the derived potentials are written in terms of the natural length that can be determined by using the derived formula. From the derived 3-D potentials, the minimum values of the front and the back surface potentials are derived and used to obtain the closed-form expressions for the front and back gate threshold voltages as functions of various device parameters and applied bias voltages. Obtained results can be found to explain the drain-induced threshold voltage roll-off and the narrow width effect of a fully depleted small geometry SOI MOSFET in a unified manner.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1481-1486
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• 2013

In this paper, a new two dimensional (2D) analytical model of a Dual Material Gate tunnel field effect transistor (DMG TFET) is presented. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expressions for surface potential and electric field are derived. The electric field distribution can be used to calculate the tunneling generation rate and numerically extract tunneling current. The results show a significant improvement of on-current and reduction in short channel effects. Effectiveness of the proposed method has been confirmed by comparing the analytical results with the TCAD simulation results.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1497-1502
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• 2013

Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ($W_{fin}$), fin height ($H_{fin}$), and doping concentration ($D_{ch}$). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.

• Journal of Electrical Engineering and Technology
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• 제9권1호
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• pp.247-253
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

• The Korean Journal of Physiology and Pharmacology
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• 제8권5호
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• pp.289-293
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• 2004

To investigate whether VacA (vacuolating toxin) produced by Helicobacter pylori Korean stain 99 induces intestinal secretion, purified VacA was added to T84 cell monolayers mounted in Ussing chambers, and electrical parameters were monitored. Mucosal addition of low pH-pretreated VacA increased short circuit current (Isc). The effect was time- and dose-dependent and saturable. The time-to-peak Isc was concentration-dependent. Chloride channel inhibitors, niflumic acid or 5-nitro-2-(3-phenylpropylamino)-benzoate (NPPB), inhibited VacA-stimulated Isc. Carbachol (CCh)-induced increase of Isc was prolonged by the addition of VacA to the mucosal side only. The effect was unaltered by the addition of niflumic acid. VacA did not show cytopathic effects. These studies indicate that VacA is a nonlethal toxin that acts in a polar manner on T84 monolayers to potentiate $Cl^-$ secretion and the response to CCh secretion without decrease in monolayer resistance. VacA may contribute to diarrhea diseases in human intestinal epithelial cells.

• 한국정보통신학회논문지
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• 제21권6호
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• pp.1069-1074
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• 2017

항복전압의 감소는 채널길이 감소에 의하여 발생하는 심각한 단채널 효과이다. 본 논문에서는 10 nm 이하 채널길이를 갖는 이중게이트 MOSFET에서 채널크기의 변화를 파라미터로 하여 채널도핑에 따른 항복전압의 변화를 고찰하였다. 이를 위하여 해석학적 전위분포에 의한 열방사 전류와 터널링 전류를 구하고 두 성분의 합으로 구성된 드레인 전류가 $10{\mu}A$가 될 때, 드레인 전압을 항복전압으로 정의하였다. 결과적으로 채널 도핑농도가 증가할수록 항복전압은 크게 증가하였다. 채널길이가 감소하면서 항복전압이 크게 감소하였으며 이를 해결하기 위하여 실리콘 두께 및 산화막 두께를 매우 작게 유지하여야만 한다는 것을 알 수 있었다. 특히 터널링 전류의 구성비가 증가할수록 항복전압이 증가하는 것을 관찰하였다.

• 한국정보통신학회논문지
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• 제16권5호
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• pp.982-988
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• 2012

본 연구에서는 이중게이트(Double Gate; DG) MOSFET에서 문턱전압과 스켈링 이론의 관계를 관찰하였다. 기존 MOSFET의 경우 채널크기에 스켈링 이론을 적용하여 전류 및 스위칭주파수를 해석하였다. 이에 본 연구에서는 이중게이트 MOSFET에서 문턱전압의 경우 스켈링 이론의 적용가능성을 관찰하기 위하여 문턱전압의 변화를 스켈링 인자에 따라 관찰하고 분석하였다. 이를 위하여 이미 검증된 포아송방정식의 해석학적 전위분포를 이용하였으며 이때 가우스함수의 전하분포를 사용하였다. 분석결과 문턱전압이 스켈링 인자에 따라 크게 변화하였으며 변화정도는 도핑농도의 스켈링에 따라 변화한다는 것을 관찰하였다. 특히 이중게이트의 특성상 채널두께 및 채널길이에 스켈링 이론을 적용할 때 가중치를 이용한 변형된 스켈링 이론을 적용함으로써 이중게이트 MOSFET에 가장 타당한 스켈링 이론에 대하여 설명할 것이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.