• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.34-37
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• 2004

Recently advancing mobile communication tools and I.T industry, semiconductor device is requested more integrated, faster operation time and more scaled-down. Because of these reasons semiconductor device is requested multilayer interconnection. For the multilayer interconnection chemical mechanical polishing (CMP) becomes one of the most useful process in semiconductor manufacturing process. In this experiment, we focus on understand the characterize and improve the CMP technology by control of slurry flow rate. Consequently, we obtain that optimal flow rate of slurry is 170ml/min, since optimal conditions are less chemical flow and performance high with good selectivity to Ta. If we apply this results to copper CMP process. it is thought that we will be able to obtain better yield.

• 대한안전경영과학회:학술대회논문집
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• 대한안전경영과학회 2008년도 춘계학술대회
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• pp.19-33
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• 2008

The study on semiconductor industrial accident in korea has been focused on frequencies of each type, employee, characteristics, cause and un-safety condition, behaviour and so on. Those attributes of semiconductor industrial accidents were usually analyzed independently, so that it was hard to provides a well-process and systematic guide lines for efficient safety management. There fore, there were a few studies based on comprehensive survey in terms of sharp-type of safe management. The questionnaire survey carried out for the workers(284) who were responsible for safety management in to center with corporate company with semiconductor industry the factor analysis showed that there were three factor of safety management. They were 1) Investment and operation and management for accident prevention, 2) Unsafe, safety management 3) General human error and behavior the industries of respondents were correlative with three group. Three Groups showed a statistically significant differences on the number of cases. Actually, the group with the larger investment and the better unsafe cause, human error a of accident prevention had a smaller cause of accident cases.

• Transactions on Electrical and Electronic Materials
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• 제7권3호
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• pp.99-102
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• 2006

The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

• Journal of the Optical Society of Korea
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• 제19권3호
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• pp.222-227
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• 2015

We propose a new and potentially integrable scheme for the realization of an all-optical binary full adder employing two XOR gates, two AND gates, and one OR gate. The XOR gate is realized using a Mach-Zehnder interferometer (MZI) based on a semiconductor optical amplifier (SOA). The AND and OR gates are based on the nonlinear properties of a semiconductor optical amplifier. The proposed scheme is driven by two input data streams and a carry bit from the previous less-significant bit order position. In our proposed design, we achieve extinction ratios for Sum and Carry output signals of 10 dB and 12 dB respectively. Successful operation of the system is demonstrated at 10 Gb/s with return-to-zero modulated signals.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.87-92
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• 2023

As the elderly population increases, the number of patients with various joint diseases, including degenerative arthritis, is steadily increasing. CPM medical devices are needed to effectively treat degenerative arthritis that is common in the elderly population. Domestic CPM medical devices have limited functions and are highly dependent on imports for expensive imported medical devices. To solve this problem, we designed a ROM measurement function using a current sensor that is not present in existing composite joint CPM medical devices. The algorithm was designed using the fact that the force caused by joint stiffness greatly increases the current flowing through the DC motor. In addition, the need for digital healthcare in the medical field is gradually expanding as the proportion of chronically ill patients increases due to the spread of the non-face-to-face economy due to COVID-19 and the aging population. Therefore, this paper aims to improve the performance of CPM medical devices by allowing real-time confirmation of rehabilitation exercise information and operation range measurement results in accordance with digital healthcare trends through a Bluetooth application developed as an Android studio.

• 반도체디스플레이기술학회지
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• 제23권2호
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• pp.76-81
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• 2024

UC Berkeley developed RISC-V, which is an open-source Instruction Set Architecture. This paper proposes a 32-bit 6-stage pipeline architecture based on the RV32I RSIC-V. The performance of the proposed 6-stage pipeline architecture is compared with the existing 32-bit 5-stage pipeline architecture also based on the RV32I processor ISA to determine the impact of the number of pipeline stages on performance. The RISC-V processor is designed in Verilog-HDL and implemented using Quartus Prime 20.1. To compare performance the Dhrystone benchmark is used. Subsequently, peripherals such as GPIO, TIMER, and UART are connected to verify operation through an FPGA. The maximum clock frequency for the 5-stage pipeline processor is 42.02 MHz, while for the 6-stage pipeline processor, it was 49.9MHz, representing an 18.75% increase.

• ETRI Journal
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• 제16권4호
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• pp.1-11
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• 1995

A GaAs power metal semiconductor field effect transistor (MESFET) operating at a voltage as low as 3.3V has been developed with the best performance for digital handheld phone. The device has been fabricated on an epitaxial layer with a low-high doped structure grown by molecular beam epitaxy. The MESFET, fabricated using $0.8{\mu}m$ design rule, showed a maximum drain current density of 330 mA/mm at $V_{gs}$ =0.5V and a gate-to-drain breakdown volt-age of 28 V. The MESFET tested at a 3.3 V drain bias and a 900 MHz operation frequency displayed an output power of 32.5-dBm and a power added efficiency of 68%. The associate power gain at 20 dBm input power and the linear gain were 12.5dB and 16.5dB, respectively. Two tone testing measured at 900.00MHz and 900.03MHz showed that a third-order intercept point is 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order intermodulation.

• 한국산업보건학회지
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• 제26권1호
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• pp.1-10
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• 2016

Objectives: The aim of this study is to review the results of exposure to chemicals and to extremely low frequency(ELF) magnetic fields generated in wafer fabrication operations in the semiconductor industry. Methods: Exposure assessment studies of silicon wafer fab operations in the semiconductor industry were collected through an extensive literature review of articles reported until the end of 2015. The key words used in the literature search were "semiconductor industry", "wafer fab", "silicon wafer", and "clean room," both singly and in combination. Literature reporting on airborne chemicals and extremely low frequency(ELF) magnetic fields were collected and reviewed. Results and Conclusions: Major airborne hazardous agents assessed were several organic solvents and ethylene glycol ethers from Photolithography, arsenic from ion implantation and extremely low frequency magnetic fields from the overall fabrication processes. Most exposures to chemicals reported were found to be far below permissible exposure limits(PEL) (10% < PEL). Most of these results were from operators who handled processes in a well-controlled environment. In conclusion, we found a lack of results on exposure to hazardous agents, including chemicals and radiation, which are insufficient for use in the estimation of past exposure. The results we reviewed should be applied with great caution to associate chronic health effects.

• 한국광학회지
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• 제14권2호
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• pp.194-199
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• 2003

FCM(Fast moving least square reproducing kernel point collocation method) 방식의 simulation tool을 이용하여 전기장으로 구동되는 초소형 전자 렌즈의 구동 특성을 조사·분석하였다. Einzel 렌즈의 retarding mode와 accelerating mode구동에서 포텐셜 분포는 유사하지만, electric field strength는 서로 다른 방향을 갖게 되어 서로 다른 형태의 전자 궤적을 보인다. 동일한 working distance에서 accelerating mode로 구동되는 전자렌즈는 retarding mode로 구동되는 경우보다 매우 높은focusing 전압을 필요로 한다.