Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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Design and Implementation of a Six-Stage Pipeline RV32I Processor Based on RISC-V Architecture

RISC-V 아키텍처 기반 6단계 파이프라인 RV32I프로세서의 설계 및 구현

  • Kyoungjin Min (Department of System Semiconductor Engineering, Sangmyung University) ;
  • Seojin Choi (Department of System Semiconductor Engineering, Sangmyung University) ;
  • Yubeen Hwang (Department of System Semiconductor Engineering, Sangmyung University) ;
  • Sunhee Kim (Department of System Semiconductor Engineering, Sangmyung University)
  • 민경진 (상명대학교 시스템반도체공학과) ;
  • 최서진 (상명대학교 시스템반도체공학과) ;
  • 황유빈 (상명대학교 시스템반도체공학과) ;
  • 김선희 (상명대학교 시스템반도체공학과)
  • Received : 2024.05.30
  • Accepted : 2024.06.21
  • Published : 2024.06.30
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Abstract

UC Berkeley developed RISC-V, which is an open-source Instruction Set Architecture. This paper proposes a 32-bit 6-stage pipeline architecture based on the RV32I RSIC-V. The performance of the proposed 6-stage pipeline architecture is compared with the existing 32-bit 5-stage pipeline architecture also based on the RV32I processor ISA to determine the impact of the number of pipeline stages on performance. The RISC-V processor is designed in Verilog-HDL and implemented using Quartus Prime 20.1. To compare performance the Dhrystone benchmark is used. Subsequently, peripherals such as GPIO, TIMER, and UART are connected to verify operation through an FPGA. The maximum clock frequency for the 5-stage pipeline processor is 42.02 MHz, while for the 6-stage pipeline processor, it was 49.9MHz, representing an 18.75% increase.

Keywords

Acknowledgement

다음의 성과는 과학기술정보통신부와 연구개발특구진흥재단이 지원하는 과학벨트지원사업으로 수행된 연구결과입니다.

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