• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.511-519
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• 2016

This paper proposes a CMOS 6-bit phase shifter with low RMS phase and amplitude errors for an X-band phased array antenna. The phase shifter combines a switched-path topology for coarse phase states and a switch-filter topology for fine phase states. The coarse phase shifter is composed of phase shifting elements, single-pole double-throw (SPDT), and double-pole double-throw (DPDT) switches. The fine phase shifter uses a switched LC filter. The phase coverage is $354.35^{\circ}$ with an LSB of $5.625^{\circ}$. The RMS phase error is < $6^{\circ}$ and the RMS amplitude error is < 0.45 dB at 8-12 GHz. The measured insertion loss is < 15 dB, and the return losses for input and output are > 13 dB at 8-12 GHz. The input P1dB of the phase shifter achieves > 11 dBm at 8-12 GHz. The current consumption is zero with a 1.2-V supply voltage. The chip size is $1.46{\times}0.83mm^2$, including pads.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.405-414
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• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.210-220
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• 2008

We review three examples (an on-chip transmission line resonator [1], a phase-locked loop [2], and an analog-to-digital converter [3]) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually separated in time or space. This paper is an attempt to present these designs in such a way that this common approach can hopefully be applied to other circuits. We note reader that this paper is not a new contribution, but a review in which we highlight the common theme from our published works [1-3]. We published a similar paper [4], which, however, used only two examples from [1] and [2]. With the newly added content from [3] in the list of our examples, the present paper offers an expanded scope.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.232-238
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• 2008

In this paper, a wideband power efficient 2.2 GHz - 4.9 GHz Medium Power Amplifier (MPA), has been designed and fabricated using $0.8{\mu}m$ SiGe BiCMOS process technology. Passive elements such as parallel-branch spiral inductor, metal-insulator-metal (MIM) capacitor and three types of resistors are all integrated in this process. This MPA is a two stage amplifier with all matching components and bias circuits integrated on-chip. A P1dB of 17.7 dBm has been measured with a power gain of 8.7 dB at 3.4 GHz with a total current consumption of 30 mA from a 3 V supply voltage at $25^{\circ}C$. The measured 3 dB bandwidth is 2.7 GHz and the maximum Power Added Efficiency (PAE) is 41 %, which are very good results for a fully integrated Medium PA. The fabricated circuit occupies a die area of $1.7mm{\times}0.8mm$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.15-21
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• 2013

In this paper, a MEMS tunable capacitor was successfully designed and fabricated using an aluminum nitride film and a gold suspended membrane with two air gap structure for commercial RF applications. Unlike conventional two-parallel-plate tunable capacitors, the proposed tunable capacitor consists of one air suspended top electrode and two fixed bottom electrodes. One fixed and the top movable electrodes form a variable capacitor, while the other one provides necessary electrostatic actuation. The fabricated tunable capacitor exhibited a capacitance tuning range of 375% at 2 GHz, exceeding the theoretical limit of conventional two-parallel-plate tunable capacitors. In case of the contact state, the maximal quality factor was approximately 25 at 1.5 GHz. The developed fabrication process is also compatible with the existing standard IC (integrated circuit) technology, which makes it suitable for on chip intelligent transceivers and radios.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• Journal of Magnetics
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• v.16 no.3
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• pp.234-239
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• 2011

Transcranial magnetic stimulation utilizes the method of controlling applied time and changing pulse by output pulse through power density control for diagnosis purposes. Transcranial magnetic stimulation can also be used in cases where diagnosis and treatment are difficult since output pulse shape can be changed. As intensity, pulse range, and pulse shape of the stimulation pulse must be changed according to lesion, the existing sine wave-shaped stimulation treatment pulse poses limitations in achieving various treatments and diagnosis. This study actualized a new method of transcranial magnetic stimulation that applies a 3 Stage 2 Switch( power semiconductor 2EA) for controlling pulse repetition rate by achieving numerous switching control of stimulation coil. Intensity, pulse range, and pulse shape of output can be freely changed to transform various treatment pulses in order to overcome limitations in stimulation treatment presented by the previous sine wave pulse shape. The method of freely changing pulse range by using 3 Stage 2 Switch discharge method is proposed. Pulse shape, composed of various pulse ranges, was created by grafting PFN (Pulsed Forming Network) through AVR AT80S8535 one-chip microprocessor technology, and application in transcranial magnetic stimulation was achieved to study the output characteristics of stimulation treatment pulse according to delaying time of the trigger signal applied in section switch.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.3
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• pp.91-95
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• 2004

The pulsed power system is widely available for use in pulse generator applications. Generally, the pulse generator is required for very short pulse width and high peak value. We have designed and fabricated our own pulsed type power system and through its use, we investigated microbe removal characteristics. This paper introduces a simple pulsed power system for removing various microbes caused by dirty water. This system includes a 2 times power supply circuit, IR2110 operated by using a fixed voltage regulator 7812 and 7805, and the switching MOSFET (Metal Oxide Semiconductor Field Effect Transistor). We can also control this process by using a PIC one chip microprocessor. As a result, we can obtain good removing characteristics of various microbes by adjusting the charging voltage, the pulse repetition rate and the electrical field inducing time.