• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.125-131
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• 2001

When the program voltage is applied to a word line, a part of the boosted channel charge in inhibited bit lines is lost due to the coupling between the string select line (SSL) and the adjacent word line. This phenomenon causes the program disturbance in the cells connected to the inhibited bit lines. This program disturbance becomes more serious, as the word line pitch is decreased. To reduce the word line coupling, the rising edge of the word-line voltage waveform was changed from a pulse step into a ramp waveform with a controlled slope. The word-line ramping circuit was composed of a timer, a decoder, a 8 b D/A converter, a comparator, and a high voltage switch pump (HVSP). The ramping voltage was generated by using a stepping waveform. The rising time and the stepping number of the word-line voltage for programming were set to $\mutextrm{m}-$ and 8, respectively,. The ramping circuit was used in a 512Mb NAND flash memory fabricated with a $0.15-\mutextrm{m}$ CMOS technology, reducing the SSL coupling voltage from 1.4V into a value below 0.4V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.136-139
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• 2004

The requirement of planarity, such as with-in-wafer nonuniformity, post thickness range, have become increasingly stringent as critical dimensions of devices are decreased and a better control of a planarity become important. The key factors influencing the planarity capability of the CMP process have been well understood through numerous related experiments. These usually include parameters such as process pressures, relative velocities, slurry temperature, polishing pad materials and polishing head structure. Many study have been done about polishing pad and its groove structure because it's considered as one of the key factors which can decide wafer uniformity directly. But, not many study have been done about polisher head structure, especially about polisher head plate design. The purpose of this paper is to know how the plate structure can affect wafer uniformity and how to deteriorate wafer yield. Furthermore, we studied several new designed plate to improve wafer uniformity and also improve wafer yield.

• Transactions on Electrical and Electronic Materials
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• v.18 no.3
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• pp.125-128
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• 2017

This study is on how ohmic area etching affects the buffer breakdown voltage of AlGaN/GaN HEMT. The surface morphology of the ohmic metal can be improved by whole etching on the ohmic area. The buffer breakdown voltages of the samples with whole etching on the ohmic area were improved by the suppression of the metal spikes formed under the ohmic contact regions during high-temperature annealing. The samples with selective etching on the ohmic area were investigated for comparison. In addition, the buffer leakage currents were measured on the different radii of the wafer, and the uniformity of the buffer leakage currents on the wafer were investigated by PL mapping measurement.

• Journal of the Korea Convergence Society
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• v.10 no.11
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• pp.85-93
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• 2019

Despite its matchless position in the global semiconductor industry, Korea has not distinguished itself in the semiconductor equipment sector. Semiconductor cleaning equipment is one of the semiconductor fabrication equipment, and it is expected to be more important along with the advancement of semiconductor fabrication processes. This study attempts to analyze technology competitiveness of major countries in the sector including Korea, and explore specialty sub-areas of the countries. For this purpose, we collected patents of semiconductor cleaning equipment during the last 10 years from the US patent database, and implemented quantitative patent analysis and co-classification network analysis. The result shows that, the US and Japan have been leading the technological progress in this sector, and Korea's competitiveness has lagged behind not only the leading countries but also its competitors and even latecomers. Therefore, intensive R&D and developing technological capabilities are needed for advancing the country's competitiveness in the sector.

• Korean Journal of Optics and Photonics
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• v.21 no.3
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• pp.111-117
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• 2010

A 780 nm monolithic individually addressable 8-beam diode laser with 10mW optical power was developed for use in a laser scanning unit. Beam to beam spacing is $30\;{\mu}m$ and an air bridge interconnection process was developed for individual operations. From electrical and optical characteristic measurements, the developed device is a suitable optical source for a high speed laser scanning unit in multi-function printing systems and laser beam printers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.34-40
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• 2012

We have developed a highly sensitive inspection technique based on an electron beam inspection for detecting the contact failure of a poly-Si plugged layer. It was difficult to distinguish the contact failure from normal landing plugs with high impedance. Normally, the thermal annealing method has been used to decrease the impedance of poly-Si plugs and this method increases the difference of charged characteristics and voltage contrast. However, the additional process made the loss of time and broke down the device characteristics. Here, the interval scanning method without thermal annealing was effectively applied to enhance the difference of surface voltage between well-contacted poly-Si plugs and incomplete contact plugs. It is extremely useful to detect the contact failures of non-annealed plug contacts with high impedance.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.67-69
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• 2006

Capacitance and loss values of pentacene MIS capacitors with different thicknesses are measured as a function of frequency for the modeling of the devices. The equivalent circuit for the ideal MIS capacitor is adopted to model the obtained admittance, so the values of $C_i,\;C_d,\;C_b$, and $R_b$ are determined for each pentacene thickness. In the loss curve, broader loss peaks are observed in measurement than the modeling results regardless of the pentacene thickness. By considering the effects of dispersive charge transport in bulk semiconductor, more accurate modeling results are obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1139-1141
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• 2006

For the bottom-contact pentacene organic thin-film transistors (OTFTs), the insertion of a thin PMMA layer $(20{\AA})$ between the pentacene and the electrode improves the electrical performances, such as carrier mobility and on-current magnitude, about 4 times larger than those of the devices without the PMMA. The performance enhancement is presumably due to the decreased contact resistance between metal and pentacene by inserting the thin PMMA layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.11-14
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• 2003

A silicon based OELD driving circuit that has a new type of column driving method is proposed to reduce the driving circuit area. In comparison with the conventional method, latches in each column are removed and one DAC (digital-to-analog converter) drives several column lines. To make the DAC operate during a specific period for the low power consumption, a simple DESG (DAC Enable Signal Generator) circuit was devised and confirmed by the simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.242-242
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• 2010

산화 알루미늄($Al_2O_3$) 박막을 p-type Czochralski(CZ) Si 위에 Remote Plasma Atomic Layer Deposition(RPALD)을 이용하여 저온 공정으로 증착하였다. Photolithography 공정으로 grid 패턴을 형성한 후 열 증착기로 알루미늄을 증착하여 MIS-IL (Metal-Insulator-Semiconductor Inversion Layer) solar cell을 제작하였다. 반응소스로는 Trimethylaluminum (TMA)과 $O_2$를 이용하였다. $Al_2O_3$ 박막의 전기적 특성 평가를 위해 MIS capacitor를 제작하여 Capacitance-voltage (C-V), Current-voltage (I-V), Interface state density ($D_{it}$)를 평가하였으며 Solar simulator를 이용하여 MIS-IL Solar cell의 Efficiency을 측정하였다.