• Journal of East Asia Management
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• v.3 no.2
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• pp.43-64
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• 2022

Exploring innovations for latecomers to catch up has been a popular concern in industry and academia. Over the last decade, more and more East Asian latecomer firms have moved beyond imitation and are delivering innovative products and services to the market. However, the semiconductor latecomers from China have limited success in catching up with more mature semiconductor firms. Our study examines how semiconductor latecomers to break through the latecomer's dilemma by innovation and achieve catch-up. We use a single-case approach for the Semiconductor Manufacturing International Corporation (SMIC) vertical development process to analysis its innovation path of catching up. The study's results showed that SMIC relied on the government's policy and funding support, and based on the strategic endurance of entrepreneurs, it persisted in technology R&D investment and independent innovation for 20 years. SMIC finally smashed the dilemma of latecomers and successfully achieved catch-up. With these findings, we believe that the path of catching up innovation for semiconductor latecomers should be equipped with independent innovation of technology, strategic leadership of entrepreneurs and support of government policies. As these factors are combined, latecomer firms' position is expected to rise and catch-up will become visible. Our study contributes to some enlightenment on the innovation path for latecomers in China and global semiconductors to achieve their catch-up.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.19-26
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• 2024

Semiconductors are considered as one of the essential technologies in modern electronic devices and systems. Thus, it is required to predict and propose the semiconductor technology development roadmap. This study describes the key semiconductor technology issues, research and development trends, and their future roadmap, in the four areas such as the semiconductor device More-Moore integration technology, system-specific application processor technology, artificial intelligence/machine learning (AI/ML) processor technology, and outside system connectivity via optical and wireless communication.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.139-145
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• 2014

Control of threshold voltage ($V_T$) by ground-plane (GP) technique for planar tunnel field-effect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For $V_T$-modulation larger than 100 mV, heavy ground doping over $1{\times}10^{20}cm^{-3}$ or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common $V_T$-control scheme when these devices are co-integrated.

• Journal of Information Display
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• v.5 no.1
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• pp.28-33
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• 2004

A high voltage NMOSFET is proposed to drive top emission organic light emitting device (OLED) used in the organic electroluminescent (EL) display on the single crystal silicon substrate. The high voltage NMOSFET can be fabricated by utilizing a simple layout technique with a standard CMOS logic process. It is clearly shown that the maximum supply voltage ($V_{DD}$) required for the pixel-driving transistor could reach 45 V through analytic and experimental methods. The high voltage NMOSFET was fabricated by using a standard 1.5 ${\mu}m$, 5 V CMOS logic process. From the measurements, we confirmed that the high voltage NMOSFET could sustain the excellent saturation characteristic up to 50 V without breakdown phenomena.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.100-105
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• 2004

The influencing factors on the OPC (optical proximity correction) results are quantitatively analyzed using OPCed L/S patterns. ${\sigma}$ values of proximity variations are measured to be 9.3 nm and 15.2 nm for PR-A and PR-B, respectively. The effect of post exposure bake condition is assessed. 16.2 nm and 13.8 nm of variations are observed. Proximity variations of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate the OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4, 13.9, and 15.2 nm are observed for the mask mean-to-targets of 0, 2 and 4 nm, respectively. The decrease the OPC grid size from 1 nm to 0.5 nm enhances the correction resolution and the OCV is reduced from 14.6 nm to 11.4 nm. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The critical dimension (CD) uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 9.9 nm and 8.7 nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved. The decrease of OPC grid size is shown to improve not only the proximity correction, but also the uniformity.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.196-200
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• 2016

We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• Journal of Korea Trade
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• v.25 no.6
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• pp.78-104
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• 2021

Purpose - Semiconductors are a significant export item for Korea that is expected to continue to contribute significantly to the Korean economy in the future. Thus, the semiconductor industry is a critical component in the 4th Industrial Revolution and is expected to continue growing as the non-face-to-face economy expands as a result of the COVID-19 pandemic. In this context, this paper aims to empirically investigate how semiconductors are imported and exported in Korea from a global supply chain perspective by analysing import and export data at the micro-level. Design/methodology - This study conducts a multifaceted analysis of the global supply chain for semiconductors and related equipment in Korea by examining semiconductor imports and exports by semiconductor type, year, target country, mode of transportation, airport/port, and domestic region, using import/export micro-data. The visualisation, flow analysis, and Bayesian Network methodologies were used to compensate for the limitations of each method. Findings - Korea is a major exporter of semiconductor memory and has the world's highest competitiveness but is relatively weak in the field of system semiconductors. The trade deficit in 'semiconductor equipment and parts' is clearly growing. As a result, continued investment in 'system semiconductors' and 'semiconductor equipment and parts' technology development is necessary to boost exports and ensure a stable supply chain. Originality/value - Few papers on semiconductor trade in Korea have been published from the perspective of the global supply chain or value chain. This study contributes to the literature in this area by focusing on import and export data for the global supply chain of the Korean semiconductor industry using a variety of approaches. It is our hope that the insights gained from this study will aid in the advancement of SCM research.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.80-82
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• 2013

White light emitting diode (LED) determined the most appropriate color temperature in reading lighting evaluated fatigue degree of eye according to color temperature. The eye fatigue degrees are determined by brightness and color temperature. Therefore, we measured the results of eyes test according to the change of color temperature and brightness. Experiments except for astigmatic corrected visual acuity of 0.8 more and age 20 to 25 years old, male and female college students was conducted in 100 patients. And constant illumination conditions, visual acuity was measured by varying the color temperature. The optometry at 10 minutes in the darkroom adapted eye. And then the temperature of $25{\pm}3$ degrees, the humidity was carried out at $50{\pm}5%$. As a result of typical color temperature of white light (5,600 K) has identification of the readability.