• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.324-327
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• 2014

Germanium (Ge) is a promising material for next generation nanoelectronics and multiple junction solar cells. This work investigated the electrical properties in Cu/p-type Ge Schottky diodes, using current-voltage (I-V) measurements. The Schottky barrier heights were 0.66, 0.59, and 0.70 eV from the forward ln(I)-V, Cheung, and Norde methods, respectively. The ideality factors were 1.92 and 1.78 from the forward ln(I)-V method and Cheung method, respectively. Such high ideality factor could be associated with the presence of an interfacial layer and interface states at the Cu/p-Ge interface. The reverse-biased current transport was dominated by the Poole-Frenkel emission rather than the Schottky emission.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.205-208
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• 2001

Schottky barrier diodes are fabricated on a intrinsic GaN(4${\mu}{\textrm}{m}$) epitaxial structure grown by rf plasma molecular beam epitaxy (MBE) on sapphire substrates. First, We make Ohmic electrodes (Ti/Al/Ti/Au) by evaporator. Next, we contact RuO$_2$ by dipping in the solution (RuCl$_3$.HClO$_4$), and then we deposit Ni/Au on the surface of RuO$_2$ by evaporator. We study the electrical characteristics of GaN Schottky barrier diodes made by these methods. Measurements are C-V, I-V, SEM, EDX, and XRD for the characteristics of devices. Thickness of RuO$_2$ layer depends on supplied voltage and dipping time. Device of thinner RuO$_2$ layer have a good Schottky characteristics compare with device of thicker RuO$_2$ layer

• Journal of the Korean Vacuum Society
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• v.16 no.3
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• pp.197-204
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• 2007

Ultra thin Er-silicide layers formed by Er deposition on the clean p-silicon and in situ post annealing technique were investigated with respect to change of the Schottky barrier height. The formation of Er silicides was confirmed by XPS results. UPS measurements revealed that the workfunction of the silicide decreased and was saturated as the deposited Er thickness increased up to $10{\AA}$. We found that the silicides were mainly composed of Er5Si3 phase through the XRD experiments. After Schottky diodes were fabricated with the Er silicide/p-Si junctions, the Schottky barrier heights were calculated $0.44{\sim}0.78eV$ from the I-V measurements of the Schottky diodes. There was large discrepancy in the Schottky barrier heights deduced from the UPS with the ideal junction condition and the real I-V measurements, so that we attributed the discrepancy to the $Er_5Si_3$ phase in the Er-silicides and the large interfacial density of trap state of it.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.3
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• pp.241-245
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• 2022

In this study, we measured and comparatively analyzed the characteristics of MPS (Merged Pin Schottky) diodes in 4H-SiC by changing the areal ratio between the Schottky and PN junction region. Increasing the temperature from 298 K to 473 K resulted in the threshold voltage shifting from 0.8 V to 0.5 V. A wider Schottky region indicates a lower on-resistance and a faster turn-on. The effective barrier height was smaller for a wider Schottky region. Additionally, the depletion layer became smaller under the influence of the reduced effective barrier height. The wider Schottky region resulted in the ideality factor being reduced from 1.37 to 1.01, which is closer to an ideal device. The leakage saturation current increased with the widening Schottky region, resulting in a 1.38 times to 2.09 times larger leakage current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.367-371
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• 2018

1,200 V class junction barrier schottky (JBS) diodes and schottky barrier diodes (SBD) were simultaneously fabricated on the same 4H-SiC wafer. The resulting diodes were characterized at temperatures from room temperature to 473 K and subsequently compared in terms of their respective I-V characteristics. The parameters deduced from the observed I-V measurements, including ideality factor and series resistance, indicate that, as the temperature increases, the threshold voltage decreases whereas the ideality factor and barrier height increase. As JBS diodes have both Schottky and PN junction structures, the proper depletion layer thickness, $R_{on}$, and electron mobility values must be determined in order to produce diodes with an effective barrier height. The comparison results showed that the JBS diodes exhibit a larger effective barrier height compared to the SBDs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.25-34
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• 2002

In this paper, silicidation induced Schottky contact area was obtained using the current voltage(I-V) characteristics of shallow cobalt silicided p+-n and n+-p junctions. In reverse bias region, Poole-Frenkel barrier lowering influenced predominantly the reverse leakage current, masking thereby the effect of Schottky contact formation. However, Schottky contact was conclusively shown to be the root cause of the modified I-V behavior of n+-p junction in the forward bias region. The increase of leakage current in silicided n+-p diodes is consistent with the formation of Schottky contact via cobalt slicide penetrating into the p-substrate or near to the junction area and generating trap sites. The increase of reverse leakage current is proven to be attributed to the penetration of silicide into depletion region in case of the perimeter intensive n+-p junction. In case of the area intensive n+-p junction, the silicide penetrated near to the depletion region. There is no formation of Schottky contact in case of the p+-n junction where no increase in the leakage current is monitored. The Schottky contact amounting to less than 0.01% of the total junction was extracted by simultaneous characterization of forward and reverse characteristics of silicided n+-p diode.

• Journal of IKEEE
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• v.19 no.1
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• pp.94-100
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• 2015

In this paper, 50V power U-MOSFET which replace the body(PN) diode with Schottky is proposed. As already known, Schottky diode has the advantage of reduced reverse recovery loss than PN diode. Thus, the power MOSFET with integrated Schottky integrated can minimize the reverse recovery loss. The proposed Schottky body diode U-MOSFET(SU-MOS) shows reduction of reverse recovery loss with the same transfer, output characteristic and breakdown voltage. As a result, 21.09% reduction in peak reverse current, 7.68% reduction in reverse recovery time and 35% improvement in figure of merit(FOM) are observed when the Schottky width is $0.2{\mu}m$ and the Schottky barrier height is 0.8eV compared to conventional U-MOSFET(CU-MOS). The device characteristics are analyzed through the Synopsys Sentaurus TCAD tool.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.377-377
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• 2012

반도체 물질로서 Zinc oxide (ZnO) nanorod (NR)는 Hydrothermal growth method로 제작 시 고가의 장비가 필요치 않기에 저비용 대면적 박막을 제작하는데 적합하지만 NR들의 array 조절과 각각의 rod와 전극 간의 연결에서 어려움을 가지고 있다. 최근 연구에서는 이러한 NR array 형상 조절과 소자의 성능 향상을 위하여 tilted sputtering method를 이용해 seed layer를 lateral 하게 형성하여 성장시켜 표면적을 극대화함으로서 응용되는 센서의 성능을 향상시키는 연구가 진행되고 있다. 본 연구에서는 이렇게 향상된 수평구조의 ZnO NR과 다양한 전극 금속 간의 schottky barrier의 높이 차이에 따라 sensitivity와 response time의 차이를 측정하였다. NR들을 전계방출형 전자현미경과 XRD로 분석 NR의 lateral structure 및 결정성을 확인하였다. 그리고 이렇게 형성한 NR을 소자화하여 Au, Ag, Al을 전극 금속물질로 사용한 경우에 대하여 sensing performance와 전극 금속의 schottky barrier의 상관관계를 확인하였다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.5
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• pp.61-66
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• 1997

In this paper we report the fabrication of an InGaAs metal-semiconductor-metal (MSM) photodiode(PD) which an InAlAs barrier enhancement layer that has very low dark current and high speed chracteristics. The detector using Cr/Au schottky metal fingers with 4um spacing on a large active area of 300*300um$^{2}$ offers a low dark current of 38nA at 10V, a low capacitance of 0.8pF, and a high 3-dB bandwidth of 2.4 GHz. To our knowledge, these characteristics are better than any previously published results obtained from large area InGaAs MSM PD's. The RC equivalent model and frequency domain current response model considering transit time were also used to analyze the frequency characteristic of the fabricated device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.348-348
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• 2010

Nanostructures have great potential in various devices due to the their promising electronic and optical properties. Nano-patterned the front surface of a solar cell generally results in improved performance, mostly due to an increase in the short-circuit current by the incident photons strike the cell surface at an angle. In this work, we investigate AFM-assisted nano-patterned field effect transistors (FETs) with vairous silicon oxide distance value D, from ${\sim}0.5{\mu}m$ to $1{\mu}m$. Also, we compared the electro-optical characteristics of the patterned FETs and the non-patterned FETs (reference device) based on both 2-dimensional simulation and experimental results for the wavelength from 100nm to 900nm. In addition, we report electric characteristics for illuminated surface in schottky barrier field effect transistors (SB-FETs).