• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.4
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• pp.33-41
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• 2006

RSA cryptosystem is of great use in systems such as IC card, mobile system, WPKI, electronic cash, SET, SSL and so on. RSA is performed through modular exponentiation. It is well known that the Montgomery multiplier is efficient in general. The critical path delay of the Montgomery multiplier depends on an addition of three operands, the problem that is taken over carry-propagation makes big influence at an efficiency of Montgomery Multiplier. Recently, the use of the Carry Save Adder(CSA) which has no carry propagation has worked McIvor et al. proposed a couple of Montgomery multiplication for an ideal exponentiation, the one and the other are made of 3 steps and 2 steps of CSA respectively. The latter one is more efficient than the first one in terms of the time complexity. In this paper, for faster operation than the latter one we use binary signed-digit(SD) number system which has no carry-propagation. We propose a new redundant binary adder(RBA) that performs the addition between two binary SD numbers and apply to Montgomery multiplier. Instead of the binary SD addition rule using in existing RBAs, we propose a new addition rule. And, we construct and simulate to the proposed adder using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is faster by a minimum 12.46% in terms of the time complexity than McIvor's 2 method and existing RBAs.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.17-24
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• 2005

This paper proposes a Decision Feedback Equalizer (DFT) with an error feedback filter for blind channel equalization. The proposed equalizer uses Least Mean Square(LMS) Algorithm and Multi-Modulus Algorithm (MMA), and has been designed for 64/256 QAM constellations. The existing MMA equalizer uses either two transversal filters or feedforward and feedback filers, while the proposed equalizer uses feedforward, feedback and error feedback filters to improve the channel adaptive performance and to reduce the number of taps. The proposed equalizer has been simulated using the $SPW^{TM}$ tool and it shows performance improvement. It has been modeled by VHDL and logic synthesis has been performed using the $0.25\;\mu m$ Faraday CMOS standard cell library. The total number of gates is about 190,000 gates. The proposed equalizer operates at 15 MHz. In addition, FPGA vertification has been performed using FPGA emulation board.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.53-60
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• 2009

A low-power/small-area 128-point FFT processor is designed, which is based on logarithmic number system (LNS) and some design techniques to minimize both hardware complexity and arithmetic error. The complex-number multiplications and additions/subtractions for FFT computation are implemented with LNS adders and look-up table (LUT) rather than using conventional two's complement multipliers and adders. Our design reduces the gate counts by 21% and the memory size by 16% when compared to the conventional two's complement implementation. Also, the estimated power consumption is reduced by about 18%. The LNS-based FFT processor synthesized with 0.35 ${\mu}m$ CMOS standard cell library has 39,910 gates and 2,880 bits memory. It can compute a 128-point FIT in 2.13 ${\mu}s$ with 60 MHz@2.5V, and has the average SQNR of 40.7 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.75-82
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• 2008

In this paper, we propose an efficient symbol detection algorithm for multiple-input multiple-output spatial multiplexing (MIMO-SM) systems and present its design and implementation results. By enhancing the performance of the first detected symbol which causes error propagation, the proposed algorithm achieves a considerable performance gain as compared to the conventional sorted QR decomposition (SQRD) based detection and the ordered successive detection (OSD) algorithms. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In case of 16QAM MIMO-SM system with 4 transmit and 4 receive ($4{\times}4$) antennas, at $BER=10^{-3}$ the proposed algorithm obtains the gai improvement of about 2.5-13.5 dB over the conventional algorithms. The proposed detection algorithm was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. The results show that the proposed algorithm can be implemented without increasing the hardware costs significantly.

• The Journal of Korean Medicine Ophthalmology and Otolaryngology and Dermatology
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• v.30 no.4
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• pp.62-74
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• 2017

Objectives : The purpose of this study is to investigate the effect of laser therapy for diabetic ulcer by using methods of systematic review. Methods : In this review, PubMed, Cochrane library, Web of Science, CNKI, CiNii, J-STAGE, NDSL and OASIS were used as the search engines. The search period is from the start date of the search engine to October 3, 2016. Randomized controlled trials(RCTs) using laser therapy for diabetic ulcer were searched and extracted by two independent researchers. Risk of bias(RoB) of Cochrane was used to assess methodological quality of studies. Results : Finally, five RCTs were selected. The follow-up period ranged from 15 days to 20 weeks. InGaAlP laser, GaAlAs laser and light emitting diode(LED) were used to treat diabetic ulcer. The clinical trials used sham laser irradiation or standard treatment as control in comparison to laser therapy. The endpoints included ulcer size, rate of healing and time to healing with follow-up period. The RCTs demonstrated therapeutic outcomes with no adverse effect. Most items of RoB were unclear and methodological quality was low. Conclusions : Our analysis suggests that laser therapy has therapeutic effects for diabetic ulcer. However, more systematic and stringent clinical trials will be required.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.268-275
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• 2020

A lightweight hardware design of self-timed ring based true random number generator (TRNG) suitable for information security applications is described. To reduce hardware complexity of TRNG, an entropy extractor with feedback structure was proposed, which minimizes the number of ring stages. The number of ring stages of the FSTR-TRNG was determined to be a multiple of eleven, taking into account operating clock frequency and entropy extraction circuit, and the ratio of tokens to bubbles was determined to operate in evenly-spaced mode. The hardware operation of FSTR-TRNG was verified by FPGA implementation. A set of statistical randomness tests defined by NIST 800-22 were performed by extracting 20 million bits of binary sequences generated by FSTR-TRNG, and all of the fifteen test items were found to meet the criteria. The FSTR-TRNG occupied 46 slices of Spartan-6 FPGA device, and it was implemented with about 2,500 gate equivalents (GEs) when synthesized in 180 nm CMOS standard cell library.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.29-39
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• 2007

RSA is one of the most popular public-key crypto-system in various applications. This paper addresses a high-speed RSA crypto-processor with modified radix-4 modular multiplication algorithm and Chinese Remainder Theorem(CRT) using Carry Save Adder(CSA). Our design takes 0.84M clock cycles for a 1024-bit modular exponentiation and 0.25M cycles for a 512-bit exponentiations. With 0.18um standard cell library, the processor achieves 365Kbps for a 1024-bit exponentiation and 1,233Kbps for two 512-bit exponentiations at a 300MHz clock rate.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.39-49
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• 2008

AEA and ARIA are next generation standard block cipher of US and Korea, respectively, and these algorithms are used in various fields including smart cards, electronic passport, and etc. This paper addresses the first efficient unified hardware architecture of AES and ARIA, and shows the implementation results with 0.25um CMOS library. We designed shared S-boxes based on composite filed arithmetic for both algorithms, and also extracted common terms of the permutation matrices of both algorithms. With the $0.25-{\mu}m$ CMOS technology, our processor occupies 19,056 gate counts which is 32% decreased size from discrete implementations, and it uses 11 clock cycles and 16 cycles for AES and ARIA encryption, which shows 720 and 1,047 Mbps, respectively.