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http://dx.doi.org/10.13089/JKIISC.2007.17.6.29

Design of high-speed RSA processor based on radix-4 Montgomery multiplier  

Koo, Bon-Seok (Attached Institute of ETRI)
Ryu, Gwon-Ho (Attached Institute of ETRI)
Chang, Tae-Joo (Attached Institute of ETRI)
Lee, Sang-Jin (Graduate School of Information Management & Security, Korea University)
Publication Information
Journal of the Korea Institute of Information Security & Cryptology / v.17, no.6, 2007 , pp. 29-39 More about this Journal
Abstract
RSA is one of the most popular public-key crypto-system in various applications. This paper addresses a high-speed RSA crypto-processor with modified radix-4 modular multiplication algorithm and Chinese Remainder Theorem(CRT) using Carry Save Adder(CSA). Our design takes 0.84M clock cycles for a 1024-bit modular exponentiation and 0.25M cycles for a 512-bit exponentiations. With 0.18um standard cell library, the processor achieves 365Kbps for a 1024-bit exponentiation and 1,233Kbps for two 512-bit exponentiations at a 300MHz clock rate.
Keywords
RSA processor; High-speed; High-radix; Chinese Remainder Theorem;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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