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Design of a high-speed DFE Equaliser of blind algorithm using Error Feedback  

Hong Ju H. (SAMSUNG Electronics)
Park Weon H. (SAMSUNG Electronics)
Sunwoo Myung H. (School of Electrical and Computer Eng., Ajou Univ.)
Oh Seong K. (SAMSUNG Electronics)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.42, no.8, 2005 , pp. 17-24 More about this Journal
Abstract
This paper proposes a Decision Feedback Equalizer (DFT) with an error feedback filter for blind channel equalization. The proposed equalizer uses Least Mean Square(LMS) Algorithm and Multi-Modulus Algorithm (MMA), and has been designed for 64/256 QAM constellations. The existing MMA equalizer uses either two transversal filters or feedforward and feedback filers, while the proposed equalizer uses feedforward, feedback and error feedback filters to improve the channel adaptive performance and to reduce the number of taps. The proposed equalizer has been simulated using the $SPW^{TM}$ tool and it shows performance improvement. It has been modeled by VHDL and logic synthesis has been performed using the $0.25\;\mu m$ Faraday CMOS standard cell library. The total number of gates is about 190,000 gates. The proposed equalizer operates at 15 MHz. In addition, FPGA vertification has been performed using FPGA emulation board.
Keywords
error feedback; DFE;
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