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Design of Bit Manipulation Accelerator fo Communication DSP  

Jeong Sug H. (Daewoo Electronics Corp.)
Sunwoo Myung H. (School of Electrical and Computer Eng., Ajou Univ)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.42, no.8, 2005 , pp. 11-16 More about this Journal
Abstract
This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.
Keywords
bit manipulation; accelerator; wireless communication; ASIP; SoC design;
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