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http://dx.doi.org/10.13089/JKIISC.2006.16.4.33

A Novel Redundant Binary Montgomery Multiplier and Hardware Architecture  

Lim Dae-Sung (Graduate School of Information Security(GSIS), Korea University)
Chang Nam-Su (Graduate School of Information Security(GSIS), Korea University)
Ji Sung-Yeon (Graduate School of Information Security(GSIS), Korea University)
Kim Sung-Kyoung (Graduate School of Information Security(GSIS), Korea University)
Lee Sang-Jin (Graduate School of Information Security(GSIS), Korea University)
Koo Bon-Seok (National Security Research Institute)
Publication Information
Journal of the Korea Institute of Information Security & Cryptology / v.16, no.4, 2006 , pp. 33-41 More about this Journal
Abstract
RSA cryptosystem is of great use in systems such as IC card, mobile system, WPKI, electronic cash, SET, SSL and so on. RSA is performed through modular exponentiation. It is well known that the Montgomery multiplier is efficient in general. The critical path delay of the Montgomery multiplier depends on an addition of three operands, the problem that is taken over carry-propagation makes big influence at an efficiency of Montgomery Multiplier. Recently, the use of the Carry Save Adder(CSA) which has no carry propagation has worked McIvor et al. proposed a couple of Montgomery multiplication for an ideal exponentiation, the one and the other are made of 3 steps and 2 steps of CSA respectively. The latter one is more efficient than the first one in terms of the time complexity. In this paper, for faster operation than the latter one we use binary signed-digit(SD) number system which has no carry-propagation. We propose a new redundant binary adder(RBA) that performs the addition between two binary SD numbers and apply to Montgomery multiplier. Instead of the binary SD addition rule using in existing RBAs, we propose a new addition rule. And, we construct and simulate to the proposed adder using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is faster by a minimum 12.46% in terms of the time complexity than McIvor's 2 method and existing RBAs.
Keywords
Montgomery multiplication; Redundant binary adder; Signed-digit system;
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  • Reference
1 H. Makino,Y. Nakase, H. Suzuki, H. Morinaka, H. Shinohara, and K. Mashiko, 'An 8.8-ns 54 ${\times}$ 54 bit multiplier with high speed redundant binary architecture', IEEE J. Solid- State Circuit, vol. 31, no. 6, pp. 773-783, June 1996   DOI   ScienceOn
2 Christof Paar, Thomas Blum, 'High radix Montgomery modular exponentiation on reconfigurable hardware', IEEE Transactions on Computers, vol. 50, No. 7, pp. 759-764, 2001   DOI   ScienceOn
3 홍종욱, 'Redundant Binary 연산을 이용한 실수/복소수 승산기', 연세대학교 대학원 석사학위 논문, 전기.컴퓨터 공학과, 1999
4 Ciaran McIvor, Maire McLoone, John V McCanny, Alan Daly, 'Fast Montgomery modular multiplication and RSA cryptographic processor architectures', ACCSC 2003, pp 379-384, 2003
5 S. E. Eldridge, C. D. Walter, 'Hardware implementation of Montgomery's modular multiplication algorithm', IEEE Transaction on Computers, Vol. 42, pp. 693-699, July 1993   DOI   ScienceOn
6 Manochehri, K, Pourmozafari. S, 'Modified radix-2 Montgomery modular multiplication to make it faster and simpler', ITCC 2005. pp. 598-602, 2004
7 A. Avizienis, 'Signed-digit number representations for fast parallel arithmetic', IRE Trans. Electron. Comput., vol. EC-IO, no. 9, pp. 389-400, Sept. 1961
8 H. Edamatsu, T. Taniguchi, T. Nishiyaina and S. Kuninobu, 'A 33 MFLOPS floating point processor using redundant binary representation', Dig. Tech. Papers of 1988 ISSCC. pp. 152-153, Feb. 1988
9 B. Kaliski, 'TWIRL and RSA Key Size', RSA Labs Tech Note, May 2003
10 Naofumi Takagi, et. al., 'High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree', IEEE Trans. on Computers, Vol. C-34, No. 9, pp. 789-796, Sep. 1985   DOI   ScienceOn
11 Walter C. D., 'Montgomery Exponentiation Needs No Final Subtractions', Electronics Letters, 35(21) : pp. 1831-1832, 1999   DOI   ScienceOn
12 SAMSUNG STD130 0.18${\mu}m$ 1.8V CMOS Standard Cell Library for Pure Logic Products
13 I. Koren, 'Computer Arithmetic Algorithms', Englewood Cliffs, NJ:Prentice-Hall, 1993