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Multi-mode Layered LDPC Decoder for IEEE 802.11n  

Na, Young-Heon (Nextchip Co., Ltd.)
Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.11, 2011 , pp. 18-26 More about this Journal
Abstract
This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.
Keywords
LDPC; error correction code; IEEE 802.11n; WLAN; min-sum algorithm; layered decoding;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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