• Journal of the Korean Society for Nondestructive Testing
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• v.24 no.2
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• pp.180-185
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• 2004

Conventional ultrasonic examination to detect micro and small surface cracks is based on the pulse-echo technique using a normal immersion focused transducer with high frequency, or an angle-beam transducer generating surface waves. It is difficult to make an automatic ultrasonic system that can detect micro and small surface cracks and position in a large structure like steel and ceramic rolls, because of the huge data of inspection and the ambiguous position data of the transducer. In this study, a high-precision scanning acoustic microscope with a 10MHz large-aperture transducer has been used to assess the existence, position and depth of a surface crack from the real-time A, B, C scans obtained by exploiting the ultrasonic diffraction. The ultrasonic method with large aperture transducer has improved the accuracy of the crack depth assessment and also the scanning speed by ten times, compared with the conventional ultrasonic methods.

• Journal of the Korean Society for Nondestructive Testing
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• v.23 no.1
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• pp.45-52
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• 2003

A number of stress corrosion cracks in turbine rotor disk keyway in power plants have been found and the necessity has been raised to detect and evaluate the cracks prior to the catastrophic failure of turbine disk. By ultrasonic RF signal analysis and using a neural network based on bark-propagation algorithm, we tried to evaluate the location, size and orientation of cracks around keyway. Because RF signals received from each reflector have a number of peaks, they were processed to have a single peak for each reflector. Using the processed RF signals, scan data that contain the information on the position of transducer and the arrival time of reflected waves from each reflector were obtained. The time difference between each reflector and the position of transducer extracted from the scan data were then applied to the back-propagation neural network. As a result, the neural network was found useful to evaluate the location, size and orientation of cracks initiated from keyway.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.73-82
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• 2005

Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of the Korean Society for Nondestructive Testing
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• v.26 no.6
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• pp.440-446
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• 2006

The reactor vessel body and closure head are fastened with the stud bolt that is one of crucial parts for safety of the reactor vessels in nuclear power plants. It is reported that the stud bolt is often experienced by fatigue cracks initiated at threads. Stud bolts are inspected by the ultrasonic technique during the overhaul periodically for the prevention of failure which leads to radioactive leakage from the nuclear reactor. The conventional ultrasonic inspection for stud bolts was mainly conducted by reflected echo method based on shadow effect. However, in this technique, there were numerous spurious signals reflected from every oblique surfaces of the thread. In this study, ultrasonic phased array technique was applied to investigate detectability of flaws in stud bolts and characteristics of ultrasonic images corresponding to different scanning methods, that is, sector and linear scan. For this purpose, simplified stud bolt specimens with artificial defects of various depths were prepared.

• ETRI Journal
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• v.44 no.5
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• pp.816-825
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• 2022

Nondestructive testing, which can monitor a product's interior without disassembly, is becoming increasingly essential for industrial inspection. Computed laminography (CL) is widely used in this application, as it can reconstruct a product, such as a printed circuit board, into a three-dimensional (3D) high-magnification image using X-rays. However, such high-magnification scanning environments can be affected by minute vibrations of the CL device, which can generate motion artifacts in the 3D reconstructed image. Since such vibrations are irregular, geometric corrections must be performed at every scan. In this paper, we propose a geometry calibration method that can correct the geometric information of CL scans based on the image without using geometry calibration phantoms. The proposed method compares the projection and digitally reconstructed radiography images to measure the geometric error. To validate the proposed method, we used both numerical phantom images at various magnifications and images obtained from real industrial CL equipment. The experiment results confirmed that sharpness and contrast-to-noise ratio (CNR) were improved.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.14-25
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• 1999

The IEEE standard 1149.1, which was proposed to increase the observability and the controllability in I/O pins, makes it possible the board level testing. In the boundary-scan environments, many shift operations are required due to their serial nature. This increases the test application time and the test application costs. To reduce the test application time, the method based on the parallel opereational multiple scan paths was proposed, but this requires the additional I/O pins and the internal wires. Moreover, it is difficult to make the designs in conformity to the IEEE standard 1149.1 since the standard does not support the parallel operation of data shifts on the scan paths. In this paper, the multiple scan path access algorithm which controls two scan paths simultaneously with one test bus is proposed. Based on the new algorithm, the new algorithm, the new board level BIST architecture which has a relatively small area overhead is developed. The new BIST architecture can reduce the test application time since it can shift the test patterns and the test responses of two scan paths at a time. In addition, it can reduce the costs for the test pattern generation and the test response analysis.

• Journal of the Korean Society for Nondestructive Testing
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• v.24 no.3
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• pp.275-281
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• 2004

Socket weldment used to change the flow direction of fluid nay have flaws such as lack of fusion and cracks. Liquid penetrant testing or Radiography testing have been applied as NDT methods for flaw detection of the socket weldment. But it is difficult to detect the flaw inside of the socket weldment with these methods. In order to inspect the flaws inside the socket weldment, a ultrasonic testing method is established and a ultrasonic transducer and automated ultrasonic testing system are developed for the inspection. The automated ultrasonic testing system is based on the portable personal computer and operated by the program based Windows 98 or 2000. The system has a pulser/receiver, 100MHz high speed A/D board, and basic functions of ultrasonic flaw detector using the program. For the automated testing, motion controller board of ISA interface type is developed to control the 4-axis scanner and a real time iC-scan image of the automated testing is displayed on the monitor. A flaws with the size of less than 1mm in depth are evaluated smaller than its actual site in the testing, but the flaws larger than 1mm appear larger than its actual size on the contrary. This tendency is shown to be increasing as the flaw size increases. h reliable and objective testing results are obtained with the developed system, so that it is expected that it can contribute to safety management and detection of repair position of pipe lines of nuclear power plants and chemical plants.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.43-48
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• 2008

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.746-753
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• 2001

GenBIST implemented in this paper is an automatic CAD tool, which can automatically generate circuitry in VerilogHDL code based on user defined information for the memory testing. While most commercial and conventional CAD tools adopt a method in which they make memory-testing algorithms as a library to generate circuitry, our tool can generate circuitry according to the user-defined algorithm, which makes application of various algorithms easier. In addition, memory BIST circuitry can be shared with other memories by supporting embedded memories in our tool. Also, extra pins for the memory testing are not requited when boundary scan technique is combined.