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An Efficient Test Data Compression/Decompression for Low Power Testing  

Chun Sunghoon (Department of Electrical and Electronic Engineering, Graduate School, Yonsei University)
Im Jung-Bin (Department of Electrical and Electronic Engineering, Graduate School, Yonsei University)
Kim Gun-Bae (Department of Electrical and Electronic Engineering, Graduate School, Yonsei University)
An Jin-Ho (Department of Electrical and Electronic Engineering, Graduate School, Yonsei University)
Kang Sungho (Department of Electrical and Electronic Engineering, Graduate School, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.2, 2005 , pp. 73-82 More about this Journal
Abstract
Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.
Keywords
Test Data Compression; Data Decompression; Low power test; Input Reduction; Scan Flip-flop Reordering;
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