• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.7-13
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• 1997

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.30-37
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• 2006

This paper presents a modified scan cell architecture to reduce the power dissipation during testing. It not only eliminates switching activities in the combinational logic during scan shifting but also reduces switching activities in the scan chain during the time. Furthermore, it limits the transitions on capture cycles. It can be made for test-per-scan BIST and employed in both single scan style and multiple scan style. Experimental results demonstrate that the proposed structure achieves the same fault coverage with lower power consumption compared to other existing BIST schemes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.582-594
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• 2016

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.39-44
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• 2008

Scan architecture is very effective design-for-testability technique that is widely used for high testability, however, it requires so much test time due to test vector shifting time. In this paper, an efficient scan test method is presented that is based on the Illinois scan architecture. The proposed method maximizes the common input effect via a scan chain selection scheme. Experimental results show the proposed method requires very short test time and small data volume by increasing the efficiency of common input effect.

• The Korean Journal of Nuclear Medicine Technology
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• v.19 no.2
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• pp.63-67
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• 2015

Purpose Among various causes that influence image quality degradation, various methods for decrease in Artifact occurred by respiration of patients are being used. Among them, this study intended to evaluate CTAC Shift correction method and additional scan compare to the Scan(Q static scan) using respiratory gated system. Materials and Methods This study was conducted on 10 patients, and used PET-CT Discovery 710 (GE Healthcare, MI, USA) and Varian's RPM system. 5.18 Mbq per kg of $^{18}F$-FDG was injected on patients, asked them to take a rest for 1 hour in the bed, and conducted test after urination. Images were visualized through Q static scan, CTAC Shift correction method, Additional scan based on the Whole body scan(WBS) with Artifact. Decrease in Artifact was compared in each image, conducted Gross Evalution, and measured changes of SUVmax. Results For image obtained through the CTAC Shift correction method through WBS with Artifact, 12~56%, Q static scan image showed 17~54% of change rate and Additional Scan showed -27~46% of change rate. In Blind Test, the CTAC Shift correction image showed the highest point with 4 points, Q static scan image showed 3.5 points, and Additional scan image showed 3.4 points. The standardized WBS scan through Oneway ANOVA and three types of Scan method showed significant difference(p<0.05), and did not show significant difference between the three Scan methods(p>0.05). However, the three Scan methods showed significant difference in Blind test. Conclusion Additional scan and Q static scan require more time than the CTAC Shift correction method, there is concern about excessive exposure to patients by CT rescan and Q static scan is difficult to apply on patients with inconsistent respiration or irregular respiration cycle due to pain. For CTAC Shift correction method, limited correction is possible and the range is limited as well. It is considered as a useful method of improving diagnostic value when hospitals use the system appropriately and develop various advantageous factors of each method.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.79-88
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• 2009

In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.