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Transition Repression Architecture for scan CEll (TRACE) in a BIST environment  

Kim In-Cheol (Department of Electrical and Electronic Engineering, Yonsei University)
Song Dong-Sup (Department of Electrical and Electronic Engineering, Yonsei University)
Kim You-Bean (Department of Electrical and Electronic Engineering, Yonsei University)
Kim Ki-Cheol (Department of Electrical and Electronic Engineering, Yonsei University)
Kang Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.6, 2006 , pp. 30-37 More about this Journal
Abstract
This paper presents a modified scan cell architecture to reduce the power dissipation during testing. It not only eliminates switching activities in the combinational logic during scan shifting but also reduces switching activities in the scan chain during the time. Furthermore, it limits the transitions on capture cycles. It can be made for test-per-scan BIST and employed in both single scan style and multiple scan style. Experimental results demonstrate that the proposed structure achieves the same fault coverage with lower power consumption compared to other existing BIST schemes.
Keywords
Low Power; Built-in Self-Test(BIST); Switching Activity; Scan Chain;
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