• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.23-29
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• 2004

In this paper, the asynchronous quasi dual-port SRAM employing a single port structure in SRAM embedded SOC (System On Chip) is proposed. External host can access the internal SRAM freely and the data on internal SRAM can be transferred to an another external circuitry without a synchronous signal of an external host, which operates as an asynchronous dual-port SRRAH The performances of the proposed circuits and control structure are verified through the simulation and we fabricated it using a 0.35um CMOS technology. As the results, the chip shows reduced area about 20% and saved power also 20% than conventional architectures.

• Journal of IKEEE
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• v.27 no.1
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• pp.65-70
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• 2023

More than 10,000 Carbon NanoTube Field Effect Transistors (CNTFETs), which have advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, and transparency, have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Three-dimensional multilayer structure of the CNTFET semiconductor chip and various CNTFET manufacturing process research increase the possibility of making the hybrid MOSFET-CNTFET semiconductor chip which combines conventional MOSFETs and CNTFETs together in a semiconductor chip. This paper discusses a methodology to design 6T binary SRAM using hybrid MOSFET-CNTFET. By utilizing the existing MOSFET SRAM or CNTFET SRAM design method, we will introduce a method of designing a hybrid MOSFET-CNTFET SRAM and compare its performance with the conventional MOSFET SRAM and CNTFET SRAM.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.25-31
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• 2009

A low power SRAM using supply voltage charge recycling (SVCR-SRAM) scheme is proposed. It divides into two SRAM cell blocks and supplies two different powers. A supplied power is $V_{DD}$ and $V_{DD}/2$. The other is $V_{DD}/2$ and GND. When N-bit cells are accessed, the charge used in N/2-bit cells with VDD and $V_{DD}/2$ is recycled in the other N/2-bit cells with $V_{DD}/2$ and GND. The SVCR scheme is used in the power consuming parts which bit line, data bus, word line, and SRAM cells to reduce dynamic power. The other parts of SRAM use $V_{DD}$ and GND to achieve high speed. Also, the SVCR-SRAM results in reducing leakage power of SRAM cells due to the body-effect. A 64K-bit SRAM ($8K{\times}8$bits) is implemented in a $0.18{\mu}m$ CMOS process. It saves 57.4% write power and 27.6% read power at $V_{DD}=1.8V$ and f=50MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.93-98
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• 2004

A low power SRAM using elevated source level memory cells is proposed to save the write power of SRAM. It reduces the swing voltages of the bit lines and data bus by elevating the source level of the memory cells from GND to $V_{T}$ and lowering the precharge level of the bit lines and data bus from $V_{DD}$ to $V_{DD}$ - $V_{T}$. It saves the write power of SRAM without area overhead and speed degradation. An SRAM with 8K${\times}$32bits is fabricated in a 0.25um CMOS process. It saves 45% of the power in write cycles at 300MHz with 2.5V. The maximum operating frequency is 330MHz.

• Journal of IKEEE
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• v.21 no.3
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• pp.260-263
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• 2017

Based on several CPU cores, an SoC including ADCs, DC-DC converter and 2M-byte SRAM is proposed in this paper. The CPU core consists of a 12-bit MENSA, a 32-bit Symmetric multi-core processor, as well as 16-bit CDSP. To eliminate the external SDRAM memory, internal 2M-byte SRAM is implemented. Because the SRAM normally occupies huge area, the parasitic components reduce the speed of SoC. In this work, the SRAM blocks are divided into small pieces to reduce the parasitic components. The proposed SoC is developed in a standard 55nm CMOS process and the speed of SoC is 200MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.10-15
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• 2012

This letter proposes a low-leakage SRAM using power-gating and voltage-level control. The power-gating scheme significantly reduces leakage power by shutting off the power supply to blank memory cell blocks. The voltage-level control scheme saves leakage power by raising the ground line voltage of SRAM cells and word line decoders in data-stored memory cell blocks. A $4K{\times}8bit$ SRAM chip was fabricated using a 1.2V $0.13{\mu}m$ CMOS process. The leakage powers are $1.23{\sim}9.87{\mu}W$ and $1.23{\sim}3.01{\mu}W$ for 0~100% memory usage in active and sleep modes, respectively. During the sleep mode, the proposed SRAM consumes 12.5~30.5% leakage power compared to the conventional SRAM.

• Journal of IKEEE
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• v.27 no.3
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• pp.327-332
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• 2023

CNTFET, which is receiving high attention as a next-generation semiconductor candidate due to its higher performance and various utilization than traditional silicon-based semiconductor devices, is having difficulty in commercialization because its unique process deviation such as CNT placement has not yet matured. To overcome this difficulty, numerous studies have been continuously conducted to take advantages of CNTFET and compensate its weakness by implementing circuits, which are less affected by process deviation due to repetitive circuit placement, into MOSFET-CNTFET based hybrid circuits. This paper compares how much the performance of the hybrid SRAM can be changed by semiconductor process variation existing in the traditional MOSFET SRAM or CNTFET SRAM. Simulation results show that, if the CNT density can be maintained between 7 and 9 per 32nm, hybrid SRAM is about 2.6 times and about 1.1 times more robust to process deviation than conventional MOSFET SRAM in read and write operations, respectively.

• Journal of IKEEE
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• v.26 no.1
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• pp.83-88
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• 2022

With high performance and wide application, a CNTFET has been attracting a lot of attention as a next-eneration semiconductor, but the manufacturing process of CNTFET has not been mature enough, which makes commercialization difficult. In order to overcome the imperfections of the CNTFET manufacturing process and to increase the possibility of commercialization, this paper analyzes the CNTFET SRAM performance variation according to the CNTFET partial density change based on the recently reported CNTFET manufacturing process. Through HSPICE circuit simulation analysis using the existing 32nm CNTFET HSPICE library file, transistors whose performance variation is less sensitive to partial CNT density are selected among the six transistors constituting the SRAM cell and acceptable CNT density range is proposed. As the result of analysis, it is found that when the CNT density of the two transistors connected to the bit line in SRAM cell changed from 6/32nm to 8/32nm, the deviation of SRAM performance is less than 9% and when the CNT density is less than 5/32nm, the SRAM delay is increased by more than 8 time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.53-56
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• 2004

This paper presents the improved burn-in method for the reliability of SRAM in MCP Semiconductor reliability is commonly improved through the burn-in process. Reliability problem is more significant in the Multi Chip Package, because of including over two devices in a package. In the SRAM-based Multi Chip Package, the failure of SRAM has a large effect on the yield and quality of the other chips - Flash Memory, DRAM, etc. So, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the current used methods. That method is effective in detecting special failure. Finally, with the composition of some kinds of methods, we could achieve the high qualify of SRAM in Multi Chip Package.