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A Low Leakage SRAM Using Power-Gating and Voltage-Level Control  

Yang, Byung-Do (College of Electrical and Computer Engineering, Chungbuk National University)
Cheon, You-So (College of Electrical and Computer Engineering, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.49, no.8, 2012 , pp. 10-15 More about this Journal
Abstract
This letter proposes a low-leakage SRAM using power-gating and voltage-level control. The power-gating scheme significantly reduces leakage power by shutting off the power supply to blank memory cell blocks. The voltage-level control scheme saves leakage power by raising the ground line voltage of SRAM cells and word line decoders in data-stored memory cell blocks. A $4K{\times}8bit$ SRAM chip was fabricated using a 1.2V $0.13{\mu}m$ CMOS process. The leakage powers are $1.23{\sim}9.87{\mu}W$ and $1.23{\sim}3.01{\mu}W$ for 0~100% memory usage in active and sleep modes, respectively. During the sleep mode, the proposed SRAM consumes 12.5~30.5% leakage power compared to the conventional SRAM.
Keywords
Low-leakage SRAM; Power-gating; SRAM; Voltage-level control;
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