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Design of the Asynchronous Quasi Dual-port SRAM Based on a Single-port Structure  

최정희 (충북대학교 정보통신공학과)
손기정 (충북대학교 정보통신공학과)
김성식 (충북대학교 정보통신공학과)
조경록 (충북대학교 정보통신공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.10, 2004 , pp. 23-29 More about this Journal
Abstract
In this paper, the asynchronous quasi dual-port SRAM employing a single port structure in SRAM embedded SOC (System On Chip) is proposed. External host can access the internal SRAM freely and the data on internal SRAM can be transferred to an another external circuitry without a synchronous signal of an external host, which operates as an asynchronous dual-port SRRAH The performances of the proposed circuits and control structure are verified through the simulation and we fabricated it using a 0.35um CMOS technology. As the results, the chip shows reduced area about 20% and saved power also 20% than conventional architectures.
Keywords
SRAM; Single Port; SOC;
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  • Reference
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