• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.98-103
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• 2003

This paper proposes new SPICE Macro-Model of Magnetic Tunnel Junction (MTJ) This Macro-Model has five I/O terminals, reproduces MTJ MR characteristics including hysteresis and behaves correctly to time varying input signals. Furthermore, this Model can be easily modified to various MTJs with different characteristics by simply varying internal parameters.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.49-55
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• 2015

The inaccuracy of the bias-dependent gate-drain overlap capacitance $C_{gdo}$ simulation in original BSIM4 and BSIM4 macro model using a diode is analyzed in detail. It is found that the accuracy of the macro model is better than of the BSIM4. However, the macro model cannot be used in the linear region. In order to remove the inaccuracy of the conventional models, a new BSIM4 macro model with a physical bias-dependent $C_{gdo}$ equation is proposed and its accuracy is validated in the full bias range.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.943-946
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• 2003

This paper proposes new SPICE Macro-Model of MTJ(Magnetic Tunnel Junction). This Macro-Model has five I/O terminals, reproduces MR characteristics including hysteresis and behaves correctly to time varying input signals. Furthermore, this Model can be easily modified to various MTJs with different characteristics by simply varying internal parameters.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.54-61
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• 1999

We suggested a macro medel for MOS transistors, which incorporates the distributed substrate resistance by using a method which utilizes external diodes on SPICE MOS model. By fitting the simulated s-parameters to the measures ones, we obtained a model set for the W=200TEX>$\mu\textrm{m}$ and L=0.8TEX>$\mu\textrm{m}$ NMOS transistor, and also analyzed the effects of distributed substrate resistance in the RF range. By comparing the physical parameters calculated from simulated s-parameters such as ac resistances and capacitances with the measured ones, we confirmed the validity of the simulation results. For the frequencies below 10GHz, it seems appropriated to use a simple macro model which utilizes the existing SPICE MOS model with junction diodes, after including one lumped resistor each for gate and substrate nodes.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.715-717
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• 1993

Resonant Inverter is analyzed by means of widely available software such a SPICE. In this paper, macro-model of RDCLI is used which is based on converter switch function rather than actual circuit configuration. Computer memory and nm time are greatly reduced compared to micro-model by using macro-model. System overall performance including control strategy and harmonic characteristics can be analyzed easily. This method is suited for stead state analysis and transition analysis at system level.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.111-114
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• 2000

Single Electron Transistor Logic (SETL) can be characterized by HSPICE simulation using a SPICE macro model. First, One unit SET is characterized by Monte-carlo simulation and then we fit SPICE macro-modeling equations to its characteristics. Second, using this unit SET, we simulate the transient characteristics of two-input NAND gate in both the static and dynamic logic schemes. The dynamic logic scheme shows more stable operation in terms of logic-swing and on/off current ratio. Also, there is a merit that we can use the SET only as current on-off switch without considering the voltage gain.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.634-636
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• 2021

In this study, we studied the macro-modeling of an feedback field-effect transistor (FBFET) using SPICE simulation. The previously presented macro-model of the FBFET is consisting of two circuits. one is charge integration circuit, and the other is current generation circuit. The previous current generation circuit has problem that can't predict performance accurately of the circuits, due to implementing only I_DS-V_GS characteristics. To solve this problem, we presents a model that can implement not only I_DS-V_GS characteristics but alos I_DS-V_DS characteristics by adding the diode in the current generation circuit.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.435-437
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• 1994

Cramped resonant DC link inverter is analyzed by widely available software such as SPICE. In this paper, the model of ACRDCL which is based on converter switch function rather than actual circuit configuration is used. Power circuit is modeled by functional transfer function and the controller is based on the macro-model. Computer memory and runtime are based reduced compared to micro-model. Overall performance including control strategy and harmonic characteristics in the steady state can be analyzed easily.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.545-546
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• 2006

The improved model that external capacitances are connected to a conventional BSIM3v3 RF Macro model with Rg and Rsub is developed in this paper. The extracted external capacitances and resistances are modeled by scalable fitting equations. The modeled S-parameters of $0.13{\mu}m$ NMOSFET agree well with measured ones from 10MHz to 10GHz, verifying the accuracy of the improved model.