• 한국초전도ㆍ저온공학회논문지
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• 제4권1호
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• pp.17-20
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• 2002

A complex single flux quantum(SFQ) circuit could be made up of various elementary cells such as JTL(Josephson transmission line), Splitter, XOR, DC/SFQ, SFQ/DC, T flip-flop, ‥‥, etc. In this work, we have designed and simulated a SFQ circuit, which consists of DC/SFQ, JTL and SFQ/DC, based on Nb/AlO$_{x}$Nb Josephson junction technology From the simulation, we could obtain the margins for various circuit parameters. And also we have successfully operated the circuit, which was fabricated with the same design, up to the input signal frequency of about 20 GHz.z.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.113-116
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• 2003

Confluence buffers and single flux quantum (SFQ) switches are essential components in constructing a high speed superconductive Arithmetic Logic Unit (ALU). In this work, we developed a SFQ confluence buffer and an SFQ switch. It is very important to optimize the circuit parameters of a confluence buffer and an SFQ switch to implement them into an ALU. The confluence buffer that we are currently using has a small bias margin of $\pm$11％. By optimizing it with a Josephson circuit simulator, we improved the design of confluence buffer. Our simulation study showed that we improved bias global margin of 10％ more than the existent confluence buffer. In simulations, the minimal bias margin was $\pm$33％. We also designed, fabricated, and tested an SFQ switch operating in a DC mode. The mask layout used to fabricate the SFQ switch was obtained after circuit optimization. The test results of our SFQ switch showed that it operated correctly and had a reasonably wide margin of $\pm$15％.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.109-110
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• 2002

The purpose of a superconductive DC/SFQ circuit is to produce a controlled number of picosecond single flux quantum pulses at the output when a slowly changing DC current is applied to the input. In this work, we have designed and simulated a DC/SFQ circuit based on Nb/Al$O_{x}$/Nb Josephson junction technology. From the simulation, we could obtain the margins for various circuit parameters. And also we have successfully operated a DC/SFQ circuit which was fabricated with the same design. The margin for the input bias current of the circuit was observed to be of $\pm$60%, which was very close to the simulated value.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.76-78
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• 2003

We have designed and tested an RSFQ (Rapid Single Flux Quantum) NDRO (Non Destructive Read Out) circuit for the development of a high speed superconducting ALU (Arithmetic Logic Unit). When designing the NDRO circuit, we used Julia, XIC and Lmeter for the circuit simulations and layouts. We obtained the simulation margins of larger than $\pm$25％. For the tests of NDRO operations, we attached the three DC/SFQ circuits and two SFQ/DC circuits to the NDRO circuit. In tests, we used an input frequency of 1 KHz to generate SFQ Pulses from DC/SFQ circuit. We measured the operation bias margin of NDRO to be $\pm$15％. The circuit was measured at the liquid helium temperature.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 학술대회 논문집
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• pp.140-142
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• 2003

We have designed a SFQ (Single Flux Quantum) D2 Cell and Inverter(NOT) for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we have used Julia, XIC and Lmeter for simulations and layouts. We obtained the circuit margin of larger than $\pm$25%. After layout, we drew chip for fabrication of SFQ D2 Cell and Inverter. We connected D2 Cell and Inverter to jtl, DC/SFQ, SFQ/DC and RS flip-flop for measurement.

• Progress in Superconductivity
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• 제4권2호
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• Progress in Superconductivity
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• 제3권1호
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• pp.17-22
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• 2001

Practical implementation of the SFQ technology in most application requires more than single-chip-level circuit complexity. Multiple chips have to be integrated with a technology that is reliable at cryogenic temperatures and supports an inter-chip data transmission speed of tens of GHz. In this work, we have studied two basic issues in building large RSFQ circuits. The first is the reliable inter-chip SFQ pulse transfer technique using Multi-Chip-Module (MCM) technology. By noting that the energy contained in an SFQ pulse is less than an attojoule, it is not very surprising that the direct transmission of a single SFQ pulse through MCM solder bump connectors can be difficult and an innovative technique is needed. The second is the recycling of the bias currents. Since RSFQ circuits are dc current biased the large RSFQ circuits need serial biasing to reduce the total amount of current input to the circuit.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.13-15
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• 1999

A Josephson sampler circuit using high-Tc superconductor (HTS) ramp-edge junctions has been designed, fabricated, and experimentally tested. It consists of five ramp-edge junctions with a stacked groundplane and is based on single-flux-quantum (SFQ) operations. The sampler was used to measure current waveforms at picosecond and microampere resolutions. We are developing a system based on the sampler for measuring the current waveform in a room-temperature sample. And measuring current flowing through wiring in a semiconductor large-scale integrated circuit is a promising application for the HTS sampler system.

• Progress in Superconductivity
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• 제1권2호
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• pp.81-84
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• 2000

A Josephson sampler circuit using high-Tc superconductor (HTS) ramp-edge junctions has been designed, fabricated, and experimentally tested. It consists of five ramp-edge junctions with a stacked groundplane and is based on single-flux-quantum (SFQ) operations. The sampler was used to measure current waveforms at picosecond and microampere resolutions. We are developing a system based on the sampler for measuring the current waveform in a room-temperature sample. And measuring current flowing through wiring in a semiconductor large-scale integrated circuit is a promising application for the HTS sampler system.

• Progress in Superconductivity
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• 제5권1호
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• pp.1-4
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• 2003

A five-year project for Nb-based single flux quantum (SFQ) circuits supported by Japan's Ministry of Economy Trade and Industry (METI) in Japan was started in September 2002. Since April 2003, the New Energy and Industrial Technology Development Organization (NEDO) has supported this Superconductor Network Device Project. The aim of the project is to improve the integration level of Nb-based SFQ circuits to several ten thousand Josephson junctions, in comparison with their starting integration level of only a few thousand junctions. Actual targets are a 20 GHz dual processor module for the servers and a 0.96 Tbps switch module for the routers. Starting in April 2003, the Nb project was merged with SFQ circuit research using a high-T$_{c}$ superconductor (HTS). The HTS research targets are a wide-band AD converter for mobile-phone base stations and a sampling oscilloscope for wide-band waveform measurements.