• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.33-37
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• 2013

In this paper, we introduce a SDRAM controller implemented on FPGA. Modern embedded system adopts SDRAM as a memory to meet the high capacity memory demands. Our SDRAM controller is written in Verilog and verified on an FPGA, demonstrating the functionality along with ARM Cortex-M0, supporting AMBA AHB.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.221-226
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• 2011

This paper presents a DTMB deinterleaver structure to reduce SDRAM power consumption. DTMB, the Chinese digital TV standard, has a deinterleaver that consists of many long delay buffers. SDRAM is used for this deinterleaver. The proposed structure pairs data and transfer a pair with an SDRAM transfer. With the reduction of the SDRAM operation number, the proposed structure can save the SDRAM power consumption by around 35%.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.22-29
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• 2006

In this paper, we present the efficient way of SDRAM accessing through the DMA(Direct Memory Access) when a microprocessor and peripheral blocks are sharing a SDRAM. The microprocessor is able to access a memory through the AMBA which is the system bus provided by ARM Corporation and DMAs are able to access a memory through their own bus. Peripheral block's reading and writing on the SDRAM memory are realized by the intermediate DMA in order to minimize times of access and addressing the memory. While the microprocessor doesn‘t access to the SDRAM aproaching other registers or occurring a hit signal for fetching program or data, the DMAs may read/write the data in the SDRAM without an interference of the AMBA. This way increases the efficient of the system and performance is more by 16.8%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1135-1140
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• 2011

This paper proposes a DTMB deinterleaver structure to reduce the SDRAM power consumption with buffer conversion and the single pointer-register structure. The DTMB deinterleaver with deep interleaving for higher performance consists of long delay buffers allocated on SDRAM. The conventional structure activates a new SDRAM row almost everytime when it reads and writes a datum. In the proposed structure, long buffers are transformed into several short buffers so that the number of row activations is reduced. The single pointer-register structure solves the problem of many pointer-registers. The experimental results show that the SDRAM power consumption can be reduced to around 37% with slight logic area reduction.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1209-1212
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• 2003

In this paper, we propose a SDRAM Controller. The SDRAM is often used a mainstream memory as embedded system memory due to its short latency, burst access and pipeline features. The proposed Controller provides essential functions for SDRAM initialization, read/write accesses, memory refresh and Burst access. Furthermore, the proposed controller is implemented in the form of SOFT IP. Therefore, it reduces the designer's effort greatly.

• The Journal of Information Technology
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• v.3 no.3
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• pp.57-65
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• 2000

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell of a 16M SDRAM installed in an Merged Memory with Logic(MML) generating the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by $0.25\mu\textrm{m}$ cell library. and verify the result of Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14N algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.42-45
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• 2002

A low power SDRAM output buffer with reduced power line noise and feedthrough current is presented. In multi I/O SDRAM output buffer, feedthrough current as well as the corresponding power dissipation are reduced utilizing proposed undershoot protection circuits. Ground bounce is minimized by the pull down driver using intelligent feedback scheme. Ground bounce noise is reduced by 66.3% and instantaneous and average power are reduced by 27.5% and 11.4%, respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.542-546
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• 2008

Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to maintain memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target applications: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we allow simultaneous accesses to different blocks thus achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result - we could achieve about 20-50% performance gain compared to the base DPSDRAM architecture.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1E
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.50-69
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• 2001

Three kinds of high-speed signaling methods for synchronous DRAM (SDRAM) bus interface channels (PC-133, Direct-Rambus, and SSTL-2) were analyzed in terms of the timing budget and the physical transmission characteristics. To analyze the SDRAM bus interface channels, loss mechanisms and the effective characteristic impedance method were reviewed and the ABCD matrix method was proposed as an analytic and yet accurate method. SPICE simulations were done to get the AC responses and the eye patterns of the three SDRAM bus interface channels for performance comparisons. Recent progress and future trend for SDRAM bus interface standards were reviewed.