Browse > Article
http://dx.doi.org/10.6109/jkiice.2011.15.5.1135

Low-Power DTMB Deinterleaver Structure Using Buffer Transformation and Single-Pointer Register Structure  

Kang, Hyeong-Ju (한국기술교육대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.15, no.5, 2011 , pp. 1135-1140 More about this Journal
Abstract
This paper proposes a DTMB deinterleaver structure to reduce the SDRAM power consumption with buffer conversion and the single pointer-register structure. The DTMB deinterleaver with deep interleaving for higher performance consists of long delay buffers allocated on SDRAM. The conventional structure activates a new SDRAM row almost everytime when it reads and writes a datum. In the proposed structure, long buffers are transformed into several short buffers so that the number of row activations is reduced. The single pointer-register structure solves the problem of many pointer-registers. The experimental results show that the SDRAM power consumption can be reduced to around 37% with slight logic area reduction.
Keywords
DTMB; deinterleaver; convolutional deinterleaver; SDRAM;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Y. Zhong, H. Yang, and A. Prabhakar, "A VLSI implementation of a FEC decoding system for DTMB(GB20600-2006) standard," Proc. Int. Conf. ASIC, pp. 926-929, 2007.
2 Micron Technology, Inc., "SDRAM system-power calculator," http://www.micron. com/support/dram/ power_calc.html
3 Z. Yang, Z. Wang, J. Wang, J. Wang, K. Peng, F. Yang, and J. Song, "Technical review for Chinese future DTTB system," IEEE Vehicular Technology Conference Fall, pp. 1-6, 2010.
4 M. Liu, M. Crussiere, J.-F. Helard, and O. P. Pasquero, "Analysis and performance comparison of DVB-T and DTMB systems for terrestrial digital TV," Proc. Int. Conf. Communication Systems, pp. 1399-1404, 2008.
5 H. Yang, Y. Zhong, and L. Yang, "An FPGA prototype of a forward error (FEC) decoder for ATSC digital TV," IEEE Trans. Consumer Electronics, vol. 45, no. 2, pp. 387-395, 1999.   DOI   ScienceOn
6 J. L. Ramsey, "Realization of optimum interleavers," IEEE Trans. Inform. Theory, vol. 16, no. 3, pp. 338-345, 1970.   DOI
7 M. Rim, "A VLSI architecture for convolutional deinterleavers," Proc. Int. Conf. Consumer Electronics, pp. 130-131, 1996.
8 Y.-N. Chang, "A multibank memory-based VLSI architecture of DVB symbol deinterleaver," IEEE Trans. Very Large Scale Integration Systems, vol. 18, no. 5, pp. 840-843, 2010.   DOI   ScienceOn
9 H.-J. Kang, H. Seo, and J. Kwak, "Area-efficient convolutional deinterleaver for mobile TV receiver," ACM Transactions on Embedded Computing Systems, to be published.