Performance Evaluation and Optimization of Dual-Port SDRAM Architecture for Mobile Embedded Systems |
Yang, Hoe-Seok
(서울대학교 전기컴퓨터공학부)
Kim, Sung-Chan (서울대학교 전기컴퓨터공학부) Park, Hae-Woo (서울대학교 전기컴퓨터공학부) Kim, Jin-Woo (서울대학교 전기컴퓨터공학부) Ha, Soon-Hoi (서울대학교 전기컴퓨터공학부) |
1 | Integrated Device Technology, "Dual port memory simplifies wireless base station design," Application Note, AN-409, Jan. 2004 |
2 | K. Patel, E. Macii, and M. Poncino, "Synthesis of partitioned shared memory architectures for energy-efficient multi-processor SoC," in Proc. DATE, pp. 10700-10701, Feb. 2004 |
3 | F. Gharsalli et al, "Unifying memory and processor wrapper architecture in multiprocessor SoC design," in Proc. ISSS, pp. 26-31, Oct. 2002 |
4 | K. Hayashi et al, "AP1000+: Architectural support of PUT/GET interface for parallelizing compiler," in Proc. ASPLOS, pp. 196-207, Oct. 1994 |
5 | T. V. Meeuwen et al, "System-level interconnect architecture exploration for custom memory organizations," in Proceedings of International Symposium on System Synthesis, pp. 13-18, Sep. 2001 |
6 | Samsung Electronics Inc, "Fusion Memory Solution OneDRAMTM," http://www.samsung.com/PressCenter/ PressRelease/PressRelease.asp?seq=20061213_0000306480 |