• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.8
• /
• pp.1-8
• /
• 2004

Experimental results are presented for gate oxide degradation, such as SILC and soft breakdown, and its effect on device parameters under negative and positive bias stress conditions using n-MOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both interface and oxide bulk traps are found to dominate the reliability of gate oxide. However, for positive gate voltage, the degradation becomes dominated mainly by interface trap. It was also found the trap generation in the gate oxide film is related to the breakage of Si-H bonds through the deuterium anneal and additional hydrogen anneal experiments. Statistical parameter variations as well as the “OFF” leakage current depend on both electron- and hole-trapping. Our results therefore show that Si or O bond breakage by tunneling electron and hole can be another origin of the investigated gate oxide degradation. This plausible physical explanation is based on both Anode-Hole Injection and Hydrogen-Released model.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.8
• /
• pp.17-27
• /
• 2000

This paper presents deposition and characterization of hydrogenated microcrystalline silicon (${\mu}c$ -Si:H) films on low cost glass substrate by Hot Wire CVD(HWCVD). The HWCVD ${\mu}c$ -Si:H films had deposition rates ranging from 2${\AA}$/sec to 35${\AA}$/sec with the variations of preparation conditions, which was 10 times higher than that of the films obtained from the conventional PECVD method. From the Raman spectroscopy, the prepared silicon films were found to be composed of the mixture of crystalline and amorphous phases. The crystalline volume fraction and average crystallite size, obtained from the Raman To mode peak near 520cm$^{-1}$, were 37-63% and 6-10 nm, respectively. The conductivity activation energy($E_a$) of the ${\mu}c$ -Si:H films, representing the difference of conduction band and Fermi level in an intrinsic semiconductors, increased from 0.22eV to 0.68eV with increasing pressure from 30mTorr to 300mTorr. The increase of $E_a$ with pressure indicates that the deposited films have properties close to intrinsic semiconductors, which is also proved with low dark conductivity of the ${\mu}c$ -Si:H deposited at 300mTorr. The tungsten concentration incorporated into films was about $6{\times}10^{16}atoms/cm^3$ in the samples prepared at wire temperature of 1800$^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.12
• /
• pp.8-14
• /
• 2011

The optimal geometry of the gate field plate in AlGaN/GaN-on-Si HEMT has been proposed using two-dimensional device simulation to achieve a high breakdown voltage for a given gate-to-drain distance. It was found that the breakdown voltage was drastically enhanced due to the reduced electric field at the gate corner when a gate field plate was employed. The electric field distribution at the gate corner and the field plate edge was investigated as functions of field plate length and insulator thickness. According to the simulation results, the electric field at the gate corner can be successfully reduced even with the field plate length of 1 ${\mu}m$. On the other hand, when the field plate length is too long, the distance between field plate and drain electrode is reduced below a critical level, which eventually lowers the breakdown voltage. The highest breakdown voltage was achieved with the field plate length of 1 ${\mu}m$. According to the simulation results varying the $SiN_x$ film thickness for the fixed field plate length of 1 ${\mu}m$, the optimum thickness range of the $SiN_x$ film was 200 - 300 nm where the electric field strength at the field plate edge counterbalances that of the gate corner.

• Journal of Life Science
• /
• v.22 no.9
• /
• pp.1180-1186
• /
• 2012

The purpose of this study was to investigate the effect of exercise preconditioning (EPC) on nerve growth factor (NGF), synapsin I, and choline acetyltransferase (ChAT) in the hippocampus of rats subjected to social isolation (SI). We randomly assigned four groups of male Sprague-Dawley (SD) rats (n=32) to the following treatments: GC: group housing control; IC: isolation control; GE: group housing exercise; IE: isolation exercise (n=8 each group). The rats underwent EPC 5 days a week for 8 weeks, and the speed of the treadmill was gradually increased (grade $0^{\circ}C$). After EPC, they were immediately subjected to SI for 8 weeks. The results showed that the protein levels of NGF, synapsin I, and ChAT in the hippocampus were significantly decreased in the IC group (p<0.05) compared with the GC group. However, these protein levels were significantly higher in the IE group (p<0.05). These results show that EPC may buffer the decline of function in the hippocampus by ameliorating the reduction in NGF, synapsin I, and ChAT induced by SI.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.10
• /
• pp.24-31
• /
• 2003

Short channel effects (SCE) of bulk MOSFET with super-steep retrograded channels (SSR), fully-depleted SOI, and double-gate MOSFET have been analyzed using a evanescent-mode analysis. Analytical equations of the characteristics scaling-length (λ) for three structures have been derived and the accuracy of the calculated λ was verified by comparing to the device simulation result. It is found that the minimum channel length should be larger than 5λ and the depletion thickness of the SSR should be around 30 nm in order to be applicable to 70 nm CMOS technology. High-$textsc{k}$ dielectric shows a limitation in scaling due to the drain-field penetration through the dielectric unless the equivalent SiO2 thickness is very thin.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.10
• /
• pp.1-8
• /
• 2003

Copper thin films were deposited on a Cu/Ta/Si substrate using the electroplating technique. Deposition rate was about 200 nm/min in proportion to current density and in inverse proportion to flow rate. Resistivity of copper thin film was approximately 2.1 ${\mu}$Ωcm and Int$\sub$(111)//Int$\sub$(200)/ ratio of copper film was 5.4 and no significant impurities were detected. After the deposition, electroplating copper films were annealed at various temperatures in a background pressure of 10$\^$-3/ torr. The resistivity of copper thin films were improved by ∼17 % and texture was improved by ∼40 % after annealing at 170$^{\circ}C$. The stress in films was not reduced much after annealing below 170$^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.2
• /
• pp.14-26
• /
• 2002

A new model for degenerate semiconductor quantum well devices was developed. In this model, the multi-subband Boltzmann transport equation was formulated by applying the Pauli exclusion principle and coupled to the Schrodinger and Poisson equations. For the solution of the resulted nonlinear system, the finite difference method and the Newton-Raphson method was used and carrier energy distribution function was obtained for each subband. The model was applied to a Si MOSFET inversion layer. The results of the simulation showed the changes of the distribution function from Boltzmann like to Fermi-Dirac like depending on the electron density in the quantum well, which presents the appropriateness of this modeling, the effectiveness of the solution method, and the importance of the Pauli -exclusion principle according to the reduced size of semiconductor devices.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
• /
• 2002.04a
• /
• pp.660-665
• /
• 2002

Mirror surface finish of Si-wafers has been achieved by rotary in-feed machining with cup-type wheels in ELID grinding. But the diameter of the workpiece is limited with the diameter of grinding wheel in the in-feed machining method. In this study, grinding experiments by the rotary surface grinding machine with straight type wheels ware conducted, by which the possible grinding area of the workpiece is independent of the diameter of the wheels. For the purpose of investigating the grinding characteristics of large scale diametrical silicon wafer, grinding conditions such as rotation speed of grinding wheels and revolution of workpieces are varied, and grinding machine used in this experiment is rotary type surface grinding n/c equipment with an ELID wit. The surface ground using the SD8000 wheels showed that mirror like surface roughness can be attained near 2 - 6 nm in Ra.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.4
• /
• pp.23-28
• /
• 2004

In this paper, the properties of Mo as PMOS gate electrodes were studied. The work-function of Mo extracted from C-V characteristic curves was appropriate for PMOS. To identify the electrical and chemical stability of Mo metal gate, the changes of work-function and EOT(Effective Oxide Thickness) values were investigated after 600, 700, 800 and 90$0^{\circ}C$ RTA(Rapid Thermal Annealing). Also it was found that Mo metal gate was stable up to 90$0^{\circ}C$ with underlying SiO$_2$through X-ray diffraction measurement. Sheet resistances of Mo metal gate obtained from 4-point probe were less than 10$\Omega$/$\square$ that was much lower than those of polysilicon.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.6
• /
• pp.64-71
• /
• 2000

An optical switch composed of identical, equally-spaced $Ti:LiNbO_3$ three-waveguides was designed and fabricated. Patterned Ti was diffused into z-cut $LiNbO_3$ substrates. $SiO_2$ buffer layer was evaporated to reduce the propagation loss of TM mode, and Al electrodes of CPW structure were built on the layer for switching of the guided beam. The optical switching phenomenon was confirmed when a beam of ${\lambda}=1.3{\mu}m$ was launched into the center waveguide and an electric field was applied to detune the three waveguides symmetrically.