• Journal of Energy Engineering
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• v.6 no.1
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• pp.104-113
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• 1997

This study aims to develop an analysis model using a commercial process simulator-ASPEN PLUS for an IGCC (Integrated Gasification Combined Cycle) system consisting a dry coal feeding, oxygen-blown entrained gasification process by Shell, a low temperature gas clean up process, a General Electric MS7001FA gas turbine, a three pressure, natural recirculation heat recovery steam generator, a regenerative, condensing steam turbine and a cryogenic air separation unit. The comparison between those results of this study and reference one done by other engineer at design conditions shows consistency which means the soundness of this model. The greater moisture contents in Illinois#6 coal causes decreasing gasifier temperature and the greater ash and sulfur content hurt system efficiency due to increased heat loss. As the results of sensitivity analysis using developed model for the parameters of gasifier operating pressure, steam/coal ratio and oxygen/coal ratio, the gasifier temperature increases while combustible gases (CO＋H2) decreases throughout the pressure going up. In the steam/coal ratio analysis, when the feeding steam increases the maximum combustible gas generation point moves to lower oxygen/coal ratio feeding condition. Finally, for the oxygen/coal ratio analysis, it shows oxygen/coal ratio 0.77 as a optimum operating condition at steam/coal feeding ratio 0.2.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.523-530
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• 2005

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.517-526
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• 2008

A one-chip DC-DC converter circuit for OLED(Organic Light-Emitting Diode) display module of automotive clusters is newly proposed. OLED panel driving voltage circuit, which is a charge-pump type, has improved characteristics in miniaturization, low cost and EMI(Electro-Magnetic Interference) compared with DC-DC converter of PWM(Pulse Width Modulator) type. By using bulk-potential biasing circuit, charge loss due to parasitic PNP BJT formed in charge pumping, is prevented. In addition, the current dissipation in start-up circuit of band-gap reference voltage generator is reduced by 42% and the layout area of ring oscillator is reduced by using a logic voltage VLP in ring oscillator circuit using VDD supply voltage. The driving current of VDD, OLED driving voltage, is over 40mA, which is required in OLED panels. The test chip is being manufactured using $0.25{\mu}m$ high-voltage process and the layout area is $477{\mu}m{\times}653{\mu}m$.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1210-1230
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• 1997

In this paper, we suggest an architecture of DS/CDMA tranceiver composed of one pilot channel used as reference and multiple traffic channels. The pilot channel-an unmodulated PN code-is used as the reference signal for synchronization of PN code and data demondulation. The coherent demodulation architecture is also exploited for the reverse link as well as for the forward link. Here are the characteristics of the suggested DS/CDMA system. First, we suggest an interlaced quadrature spreading(IQS) method. In this method, the PN coe for I-phase 1st channel is used for Q-phase 2nd channels and the PN code for Q-phase 1st channel is used for I-phase 2nd channel, and so on-which is quite different from the eisting spreading schemes of DS/CDMA systems, such as IS-95 digital CDMA cellular or W-CDMA for PCS. By doing IQS spreading, we can drastically reduce the zero crossing rate of the RF signals. Second, we introduce an adaptive threshold setting for the synchronization of PN code, an initial acquistion method that uses a single PN code generator and reduces the acquistion time by a half compared the existing ones, and exploit the state machines to reduce the reacquistion time Third, various kinds of functions, such as automatic frequency control(AFC), automatic level control(ALC), bit-error-rate(BER) estimator, and spectral shaping for reducing the adjacent channel interference, are introduced to improve the system performance. Fourth, we designed and implemented the DS/CDMA MODEM to be used for variable transmission rate applications-from 16Kbps to 1.024Mbps. We developed and confirmed the DS/CDMA MODEM architecture through mathematical analysis and various kind of simulations. The ASIC design was done using VHDL coding and synthesis. To cope with several different kinds of applications, we developed transmitter and receiver ASICs separately. While a single transmitter or receiver ASC contains three channels (one for the pilot and the others for the traffic channels), by combining several transmitter ASICs, we can expand the number of channels up to 64. The ASICs are now under use for implementing a line-of-sight (LOS) radio equipment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Investigative Magnetic Resonance Imaging
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• v.13 no.1
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• pp.31-39
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• 2009

Purpose : This study proposes the keyhole method in order to improve the time resolution of the proton resonance frequency(PRF) MR temperature monitoring technique. The values of Root Mean Square (RMS) error of measured temperature value and Signal-to-Noise Ratio(SNR) obtained from the keyhole and full phase encoded temperature images were compared. Materials and Methods : The PRF method combined with GRE sequence was used to get MR temperature images using a clinical 1.5T MR scanner. It was conducted on the tissue-mimic 2% agarose gel phantom and swine's hock tissue. A MR compatible coaxial slot antenna driven by microwave power generator at 2.45GHz was used to heat the object in the magnetic bore for 5 minutes followed by a sequential acquisition of MR raw data during 10 minutes of cooling period. The acquired raw data were transferred to PC after then the keyhole images were reconstructed by taking the central part of K-space data with 128, 64, 32 and 16 phase encoding lines while the remaining peripheral parts were taken from the 1st reference raw data. The RMS errors were compared with the 256 full encoded self-reference temperature image while the SNR values were compared with the zero filling images. Results : As phase encoding number at the center part on the keyhole temperature images decreased to 128, 64, 32 and 16, the RMS errors of the measured temperature increased to 0.538, 0.712, 0.768 and 0.845$^{\circ}C$, meanwhile SNR values were maintained as the phase encoding number of keyhole part is reduced. Conclusion : This study shows that the keyhole technique is successfully applied to temperature monitoring procedure to increases the temporal resolution by standardizing the matrix size, thus maintained the SNR values. In future, it is expected to implement the MR real time thermal imaging using keyhole method which is able to reduce the scan time with minimal thermal variations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• The Korean Journal of Nuclear Medicine Technology
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• v.22 no.2
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• pp.84-87
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• 2018

Purpose The radiopharmaceutical used in the nuclear medicine department is used only for the specific patient according to the prescription or instruction of the doctor without selling, so it is dispensed and it is distributed and used for the examination. Radiopharmaceuticals administered to patients should be managed appropriately as well as radiation safety management during dispensation. The purpose of this study is to investigate microbial contamination during dispensation of radiopharmaceuticals Materials and Methods This study distinguished between general workbench and clean workbench and performed three tests. First, microbial cultivation test of radiopharmaceutical prepared and dispensed in general workbenches and sterile workbenches were carried out five times, respectively. The second test was performed settle plate method three times before and after the use of the exhaust filter. Finally, Adenosine Triphosphate (ATP) measurement was performed in each workbench to measure bacterial counts. In addition, ATP measurement were carried out by designating locations and items that may be contaminated during dispensation. Results In the microbial culture test, no microorganisms were detected in both samples. In the settle plate method, it was detected without using of the exhaust filter in a general workbench once. In the ATP measurement test, it was measured at the level of 400 RLU or less, which is the standard value of contamination, in both workbenches surface. In additional ATP measurement test, the refrigerator handle in the distribution room was measured above the reference value of 1217 RLU, the vacuum vial shield of the Tech Generator at 435 RLU, and the syringe holder at 1357 RLU. After environmental disinfection, the results were reduced to 311 RLU, 136 RLU, and 291 RLU. Conclusion No contamination by bacteria was found in both workbenches. However, microbial contamination may occur if the use of an exhaust filter or proper hand hygiene is not achieved. Regular inspections and management for aseptic processing themselves will be necessary.

• Journal of the Korean Society of Radiology
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• v.17 no.4
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• pp.489-495
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• 2023

Radiation shielding facilities are constructed in locations where diagnostic radiation generators are installed, with the aim of preventing exposure for patients and radiation workers. The purpose of this study is seek to compare and validate the trend of attenuation thickness of lead, the primary material in these radiation shielding facilities, at different maximum tube voltages by Monte Carlo simulations and measurement. We employed the Monte Carlo N-Particle 6 simulation code. Within this simulation, we set a lead shielding arrangement, where the distance between the source and the lead sheet was set at 100 cm and the field of view was set at 10 × 10 cm². Additionally, we varied the tube voltages to encompass 80, 100, 120, and 140 kVp. We calculated energy spectra for each respective tube voltage and applied them in the simulations. Lead thicknesses corresponding to attenuation rates of 50, 70, 90, and 95% were determined for tube voltages of 80, 100, 120, and 140 kVp. For 80 kVp, the calculated thicknesses for these attenuation rates were 0.03, 0.08, 0.21, and 0.33 mm, respectively. For 100 kVp, the values were 0.05, 0.12, 0.30, and 0.50 mm. Similarly, for 120 kVp, they were 0.06, 0.14, 0.38, and 0.56 mm. Lastly, at 140 kVp, the corresponding thicknesses were 0.08, 0.16, 0.42, and 0.61 mm. Measurements were conducted to validate the calculated lead thicknesses. The radiation generator employed was the GE Healthcare Discovery XR 656, and the dosimeter used was the IBA MagicMax. The experimental results showed that at 80 kVp, the attenuation rates for different thicknesses were 43.56, 70.33, 89.85, and 93.05%, respectively. Similarly, at 100 kVp, the rates were 52.49, 72.26, 86.31, and 92.17%. For 120 kVp, the attenuation rates were 48.26, 71.18, 87.30, and 91.56%. Lastly, at 140 kVp, they were measured 50.45, 68.75, 89.95, and 91.65%. Upon comparing the simulation and experimental results, it was confirmed that the differences between the two values were within an average of approximately 3%. These research findings serve to validate the reliability of Monte Carlo simulations and could be employed as fundamental data for future radiation shielding facility construction.