• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.417-422
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• 2021

In this paper, a ZQ calibration using a time domain comparator is proposed. The proposed comparator is designed based on VCO, and an additional clock generator is used to reduce power consumption. By using the proposed comparator, the reference voltage and the PAD voltage were compared with a low 1 LSB voltage, so that the additional offset cancelation process could be omitted. The proposed time domain comparator-based ZQ calibration circuit was designed with a 65nm CMOS process with 1.05V and 0.5V supply voltages. The proposed clock generator reduces power consumption by 37% compared to a single time domain comparator, and the proposed ZQ calibration increases the mask margin by up to 67.4%.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.37 no.7
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• pp.875-881
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• 2013

The failure of a bolted joint owing to stress corrosion cracking (SCC) has been considered one of the most important structural integrity issues in a nuclear power plant. In this study, the failure possibility of bolting, which is used to support the steam generator of a pressurized water reactor, owing to SCC and brittle fracture was evaluated in accordance with guidelines proposed by the Electric Power Research Institute, which are called the Reference Flaw Factor method. For this evaluation, first, detailed finite element stress analyses were conducted to obtain the actual nominal stresses of bolting in which either service loads or bolt preloads were considered. Based on these nominal stresses, the structural integrity of bolting was addressed from the viewpoints of SCC and toughness. In addition, the accuracy of the EPRI Reference Flaw Factor for assessing bolting failure was investigated using finite element fracture mechanics analyses.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.619-628
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• 2019

In this paper, we designed a beta ray sensor for a true random number generator. Instead of biasing the gate of the PMOS feedback transistor to a DC voltage, the current flowing through the PMOS feedback transistor is mirrored through a current bias circuit designed to be insensitive to PVT fluctuations, thereby minimizing fluctuations in the signal voltage of the CSA. In addition, by using the constant current supplied by the BGR (Bandgap Reference) circuit, the signal voltage is charged to the VCOM voltage level, thereby reducing the change in charge time to enable high-speed sensing. The beta ray sensor designed with 0.18㎛ CMOS process shows that the minimum signal voltage and maximum signal voltage of the CSA circuit which are resulted from corner simulation are 205mV and 303mV, respectively. and the minimum and maximum widths of the pulses generated by comparing the output signal through the pulse shaper with the threshold voltage (VTHR) voltage of the comparator, were 0.592㎲ and 1.247㎲, respectively. resulting in high-speed detection of 100kHz. Thus, it is designed to count up to 100 kilo pulses per second.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.486-495
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• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.59-65
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• 2004

A stable reference voltage generator is necessary to the infrared image signal readout circuit(ROIC) to improve noise characteristics of signal originated from infrared devices, that is, to gain good images. In this paper, bandgap circuit operating at cryogenic temperature of 77K for Infrared image ROIC(readout integrated circuit) was first made. It demonstrates practical use possibility through taking measurements and estimations. Bandgap circuit is a representative voltage reference circuit. Most of bandgap reference circuits which are presented so far operate at room temperature, and their characteristic are not suitable for infrared image ROIC operating at liquid nitrogen temperature, 77K. To design bandgap circuit operating at cryogenic temperature, suitable circuit is selected and the parameter characteristics of used devices as temperature change are seen by a theoretical study and fitted at liquid temperature with considering such characteristics. This circuit has been fabricated in the Hynix 0.6um standard CMOS process, and the output voltage measured shows that the stability is 1.042±0.0015V over the temperature range of 60K to 110K and is better than bandgap circuits operated at room temperature.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2000.06a
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• pp.263-268
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• 2000

In this paper, a new indirect feedback active noise control (ANC) scheme based on the fundamental frequency estimation is proposed for systems with a harmonic noise. When reference signals necessary for feedforward ANC configuration is difficult to obtain, the conventional ANC algorithms for multi-tonal noise do not measure the reference signals but generate them with the estimated frequencies. However, the beating phenomena, in which certain frequency components of the noise vanish intermittently, may make the adaptive frequency estimation difficult. The confusion in the estimated frequencies due to the beating phenomena makes the generated reference signals worthless. The proposed algorithm consists of two parts. The first part is a reference generator using the fundamental frequency estimation and the second one is the conventional feedforward control. We propose the fundamental frequency estimation algorithm using decision rules, which is insensitive to the beating phenomena. In addition, the proposed fundamental frequency estimation algorithm has good tracking capability and lower variance of frequency estimation error than that of the conventional cascade ANF method. We are also able to control all interested modes of the noise, even which cannot be estimated by the conventional frequency estimation method because of the poor SIN ratio. We verify the performance of the proposed ANC method through simulations for the measured cabin noise of a passenger ship and the measured time-varying engine booming noise of a passenger vehicle.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1693-1698
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• 2015

This paper proposed a PFM(pulse-frequency modulator) boost converter which has dual pulse-width. The PFM boost converter is composed of BGR(band gap voltage reference generating circuit), voltage reference generating circuit, soft-start circuit, error amplifier, high-speed comparator, inductor current sensing circuit and pulse-width generator. Converter has different inductor peak current so it has wider load current range and smaller output voltage ripple. Proposed PFM boost converter generates 18V output voltage with input voltage of 3.7V and it has load current range of 0.1~300mA. Simulation results show 0.43% output voltage ripple at ligh load mode and 0.79% output voltage ripple at heavy load mode. Converter has efficiency 85% at light lode mode and it has maximum 86.4% at 20mA load current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• Journal of Biomedical Engineering Research
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• v.28 no.4
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• pp.539-548
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• 2007

In the paper, a wireless charger with the function of auto-shutdown for fully implantale middle ear hearing devices (F-IMEHD) has been designed. The wireless charger can communicate with an implant module to be turned off automatically shutdown after an internal rechargeable battery has been fully-charged by electromagnetic coupling using two coils. For the communication with an implant module, the wireless charger uses the load shift keying (LSK) method. But, the variation of the mutual inductance due to the different distance between two coils can cause the communication error in receiving the fully-charged signal from an implant module. To solve the problem, the implemented wireless charger has a variable reference generator for LSK communication. The wireless charger generates proper level of the reference voltage for a comparator using an ADC (analog-to-digital converter) and a DAC (digital-to-analog converter). Through the result of experiment, it has been confirmed that the presented wireless charger can detect signals from implantable module. And wireless charger can stop generating electromagnetic flux after an implanted battery has been fully charged in spite of variable coil distance according to different skin thickness.