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A Low-power EEPROM design for UHF RFID tag chip  

Yi, Won-Jae (창원대학교)
Lee, Jae-Hyung (창원대학교)
Park, Kyung-Hwan (한국전자통신연구원)
Lee, Jung-Hwan (매그너칩반도체)
Lim, Gyu-Ho (창원대학교)
Kang, Hyung-Geun (창원대학교)
Ko, Bong-Jin (창원대학교)
Park, Mu-Hun (창원대학교)
Ha, Pan-Bong (창원대학교)
Kim, Young-Hee (창원대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.10, no.3, 2006 , pp. 486-495 More about this Journal
Abstract
In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.
Keywords
RFID; EEPROM; Low-power; Sense amplifier;
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